^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2022 Rockchip Electronics Co. Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Elaine Zhang <zhangqing@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1106_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define _DT_BINDINGS_CLK_ROCKCHIP_RV1106_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /* pll clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define PLL_APLL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define PLL_DPLL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define PLL_CPLL 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define PLL_GPLL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define ARMCLK 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* clk (clocks) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PCLK_DDRPHY 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PCLK_DDR_ROOT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PCLK_DDRMON 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CLK_TIMER_DDRMON 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PCLK_DDRC 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PCLK_DFICTRL 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define ACLK_DDR_ROOT 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define ACLK_SYS_SHRM 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define HCLK_NPU_ROOT 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define ACLK_NPU_ROOT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PCLK_NPU_ROOT 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define HCLK_RKNN 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define ACLK_RKNN 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PCLK_ACODEC 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MCLK_ACODEC_TX 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CLK_CORE_CRYPTO 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CLK_PKA_CRYPTO 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define ACLK_CRYPTO 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define HCLK_CRYPTO 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define ACLK_DECOM 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PCLK_DECOM 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DCLK_DECOM 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define ACLK_DMAC 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PCLK_DSM 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MCLK_DSM 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CCLK_SRC_EMMC 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define HCLK_EMMC 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PCLK_GPIO4 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define DBCLK_GPIO4 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PCLK_I2C0 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CLK_I2C0 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PCLK_I2C2 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CLK_I2C2 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PCLK_I2C3 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CLK_I2C3 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PCLK_I2C4 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CLK_I2C4 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define HCLK_I2S0 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PCLK_DFT2APB 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define HCLK_IVE 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define ACLK_IVE 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PCLK_PWM0_PERI 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CLK_PWM0_PERI 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CLK_CAPTURE_PWM0_PERI 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define PCLK_PERI_ROOT 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define ACLK_PERI_ROOT 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define HCLK_PERI_ROOT 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define CLK_TIMER_ROOT 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define ACLK_BUS_ROOT 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define HCLK_SFC 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SCLK_SFC 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define PCLK_UART0 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define CLK_PVTM_CORE 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define PCLK_UART1 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define CLK_CORE_MCU_RTC 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define PCLK_PWM1_PERI 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define CLK_PWM1_PERI 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define CLK_CAPTURE_PWM1_PERI 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define PCLK_PWM2_PERI 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define CLK_PWM2_PERI 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define CLK_CAPTURE_PWM2_PERI 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define HCLK_BOOTROM 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define HCLK_SAI 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MCLK_SAI 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define PCLK_SARADC 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define CLK_SARADC 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define PCLK_SPI1 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define CLK_SPI1 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define PCLK_STIMER 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define CLK_STIMER0 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define CLK_STIMER1 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define PCLK_TIMER 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define CLK_TIMER0 84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define CLK_TIMER1 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define CLK_TIMER2 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define CLK_TIMER3 87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define CLK_TIMER4 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define CLK_TIMER5 89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define HCLK_TRNG_NS 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define HCLK_TRNG_S 91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define PCLK_UART2 92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define HCLK_CPU 93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define PCLK_UART3 94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define CLK_CORE_MCU 95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define PCLK_UART4 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define PCLK_DDR_HWLP 97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define PCLK_UART5 98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define ACLK_USBOTG 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define CLK_REF_USBOTG 101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define CLK_UTMI_USBOTG 102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define PCLK_USBPHY 103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define CLK_REF_USBPHY 104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define PCLK_WDT_NS 105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define TCLK_WDT_NS 106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define PCLK_WDT_S 107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define TCLK_WDT_S 108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define CLK_DDR_FAIL_SAFE 109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define XIN_OSC0_DIV 110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define CLK_DEEPSLOW 111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define PCLK_PMU_GPIO0 112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define DBCLK_PMU_GPIO0 113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define CLK_PMU 114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define PCLK_PMU 115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define PCLK_PMU_HP_TIMER 116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define CLK_PMU_HP_TIMER 117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define CLK_PMU_32K_HP_TIMER 118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define PCLK_I2C1 119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define CLK_I2C1 120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define PCLK_PMU_IOC 121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define PCLK_PMU_MAILBOX 122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define CLK_PMU_MCU 123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define CLK_PMU_MCU_RTC 124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define CLK_PMU_MCU_JTAG 125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define CLK_PVTM_PMU 126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define PCLK_PVTM_PMU 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define CLK_REFOUT 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define CLK_100M_PMU 129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define PCLK_PMU_ROOT 130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define HCLK_PMU_ROOT 131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define HCLK_PMU_SRAM 132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define PCLK_PMU_WDT 133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define TCLK_PMU_WDT 134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define CLK_DFICTRL 135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define CLK_DDRMON 136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define CLK_DDR_PHY 137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define ACLK_DDRC 138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define CLK_CORE_DDRC_SRC 139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define CLK_CORE_DDRC 140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define CLK_50M_SRC 141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define CLK_100M_SRC 142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define CLK_150M_SRC 143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define CLK_200M_SRC 144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define CLK_250M_SRC 145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define CLK_300M_SRC 146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define CLK_339M_SRC 147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define CLK_400M_SRC 148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define CLK_450M_SRC 149
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define CLK_500M_SRC 150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define CLK_I2S0_8CH_TX_SRC 151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define CLK_I2S0_8CH_TX_FRAC 152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define CLK_I2S0_8CH_TX 153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define CLK_I2S0_8CH_RX_SRC 154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define CLK_I2S0_8CH_RX_FRAC 155
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define CLK_I2S0_8CH_RX 156
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define I2S0_8CH_MCLKOUT 157
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define MCLK_I2S0_8CH_RX 158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define MCLK_I2S0_8CH_TX 159
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define CLK_REF_MIPI0_SRC 160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define CLK_REF_MIPI0_FRAC 161
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define CLK_REF_MIPI0_OUT 162
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define CLK_REF_MIPI1_SRC 163
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define CLK_REF_MIPI1_FRAC 164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define MCLK_REF_MIPI0 165
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define MCLK_REF_MIPI1 166
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define CLK_REF_MIPI0 167
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define CLK_REF_MIPI1 168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define CLK_UART0_SRC 169
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define CLK_UART0_FRAC 170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define CLK_UART0 171
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define SCLK_UART0 172
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define CLK_UART1_SRC 173
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define CLK_UART1_FRAC 174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define CLK_UART1 175
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define SCLK_UART1 176
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define CLK_UART2_SRC 177
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define CLK_UART2_FRAC 178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define CLK_UART2 179
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define SCLK_UART2 180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define CLK_UART3_SRC 181
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define CLK_UART3_FRAC 182
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define CLK_UART3 183
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define SCLK_UART3 184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define CLK_UART4_SRC 185
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define CLK_UART4_FRAC 186
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define CLK_UART4 187
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define SCLK_UART4 188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define CLK_UART5_SRC 189
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define CLK_UART5_FRAC 190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define CLK_UART5 191
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define SCLK_UART5 192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define CLK_VICAP_M0_SRC 193
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define CLK_VICAP_M0_FRAC 194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define CLK_VICAP_M0 195
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define SCLK_VICAP_M0 196
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define CLK_VICAP_M1_SRC 197
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define CLK_VICAP_M1_FRAC 198
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define CLK_VICAP_M1 199
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define SCLK_VICAP_M1 200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define DCLK_VOP_SRC 201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define PCLK_CRU 202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define PCLK_TOP_ROOT 203
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define PCLK_SPI0 204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define CLK_SPI0 205
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define SCLK_IN_SPI0 206
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define CLK_UART_DETN_FLT 207
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define HCLK_VEPU 208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define ACLK_VEPU 209
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define CLK_CORE_VEPU 210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define CLK_CORE_VEPU_DVBM 211
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define PCLK_GPIO1 212
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define DBCLK_GPIO1 213
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define HCLK_VEPU_PP 214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define ACLK_VEPU_PP 215
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define HCLK_VEPU_ROOT 216
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define ACLK_VEPU_COM_ROOT 217
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define ACLK_VEPU_ROOT 218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define PCLK_VEPU_ROOT 219
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define PCLK_VICAP_VEPU 220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define PCLK_CSIHOST0 221
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define CLK_RXBYTECLKHS_0 222
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define PCLK_CSIHOST1 223
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define CLK_RXBYTECLKHS_1 224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define PCLK_GPIO3 225
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define DBCLK_GPIO3 226
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define HCLK_ISP3P2 227
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define ACLK_ISP3P2 228
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define CLK_CORE_ISP3P2 229
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define PCLK_MIPICSIPHY 230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define CCLK_SRC_SDMMC 231
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define HCLK_SDMMC 232
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define CLK_SDMMC_DETN_FLT 233
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define HCLK_VI_ROOT 234
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define ACLK_VI_ROOT 235
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define PCLK_VI_ROOT 236
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define PCLK_VI_RTC_ROOT 237
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define PCLK_VI_RTC_TEST 238
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define PCLK_VI_RTC_PHY 239
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define DCLK_VICAP 240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define PCLK_VICAP 241
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define ACLK_VICAP 242
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define HCLK_VICAP 243
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define I0CLK_VICAP 244
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define I1CLK_VICAP 245
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define RX0PCLK_VICAP 246
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define RX1PCLK_VICAP 247
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define ISP0CLK_VICAP 248
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define PCLK_GPIO2 249
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define DBCLK_GPIO2 250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define ACLK_MAC 251
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define PCLK_MAC 252
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define CLK_GMAC0_50M_O 253
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define CLK_GMAC0_TX_50M_O 254
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define CLK_GMAC0_REF_50M 255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define CLK_GMAC0_TX_50M 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define CLK_GMAC0_RX_50M 257
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define ACLK_MAC_ROOT 258
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define CLK_MACPHY 259
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define CLK_OTPC_ARB 260
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define PCLK_OTPC_NS 261
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define CLK_SBPI_OTPC_NS 262
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define CLK_USER_OTPC_NS 263
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define PCLK_OTPC_S 264
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define CLK_SBPI_OTPC_S 265
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define CLK_USER_OTPC_S 266
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define PCLK_OTP_MASK 267
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define CLK_PMC_OTP 268
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define HCLK_RGA2E 269
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define ACLK_RGA2E 270
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define CLK_CORE_RGA2E 271
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define CCLK_SRC_SDIO 272
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define HCLK_SDIO 273
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define PCLK_TSADC 274
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define CLK_TSADC 275
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define CLK_TSADC_TSEN 276
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define ACLK_VO_ROOT 277
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define HCLK_VO_ROOT 278
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define PCLK_VO_ROOT 279
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define ACLK_VOP_ROOT 280
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define HCLK_VOP 281
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define DCLK_VOP 282
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define ACLK_VOP 283
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define CLK_RTC_32K 284
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define PCLK_MAILBOX 291
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define CLK_NR_CLKS (PCLK_MAILBOX + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define SCLK_EMMC_DRV 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define SCLK_EMMC_SAMPLE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define SCLK_SDMMC_DRV 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define SCLK_SDMMC_SAMPLE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define SCLK_SDIO_DRV 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define SCLK_SDIO_SAMPLE 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define CLK_NR_GRF_CLKS (SCLK_SDIO_SAMPLE + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /********Name=PMUSOFTRST_CON00,Offset=0xA00********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define SRST_P_I2C1 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define SRST_I2C1 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define SRST_H_PMU_BIU 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define SRST_P_PMU_BIU 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define SRST_H_PMU_SRAM 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define SRST_PMU_MCU 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define SRST_PMU_MCU_PWRUP 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define SRST_PMU_MCU_CPU 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define SRST_T_PMU_MCU_CPU 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /********Name=PMUSOFTRST_CON01,Offset=0xA04********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define SRST_P_PMU_GPIO0 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define SRST_PMU_GPIO0 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define SRST_PVTM_PMU 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define SRST_P_PVTM_PMU 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define SRST_DDR_FAIL_SAFE 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /********Name=PMUSOFTRST_CON02,Offset=0xA08********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define SRST_P_PMU_HP_TIMER 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define SRST_PMU_HP_TIMER 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define SRST_PMU_32K_HP_TIMER 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define SRST_P_PMU_IOC 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define SRST_P_PMU_CRU 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define SRST_P_PMU_GRF 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define SRST_P_PMU_SGRF 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define SRST_P_PMU_SGRF_REMAP 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define SRST_P_PMU_WDT 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define SRST_T_PMU_WDT 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define SRST_P_PMU_MAILBOX 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define SRST_WRITE_ENABLE 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /********Name=SOFTRST_CON02,Offset=0x10A08********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define SRST_REF_PVTPLL_0 262183
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define SRST_REF_PVTPLL_1 262184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define SRST_P_CRU 262186
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define SRST_P_CRU_BIU 262187
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /********Name=PERISOFTRST_CON00,Offset=0x12A00********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define SRST_P_PERI_BIU 294916
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define SRST_A_PERI_BIU 294917
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define SRST_H_PERI_BIU 294918
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define SRST_H_BOOTROM 294919
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define SRST_P_TIMER 294920
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define SRST_TIMER0 294921
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define SRST_TIMER1 294922
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define SRST_TIMER2 294923
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define SRST_TIMER3 294924
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define SRST_TIMER4 294925
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define SRST_TIMER5 294926
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define SRST_P_STIMER 294927
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /********Name=PERISOFTRST_CON01,Offset=0x12A04********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define SRST_STIMER0 294928
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define SRST_STIMER1 294929
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define SRST_P_WDT_NS 294930
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define SRST_T_WDT_NS 294931
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define SRST_P_WDT_S 294932
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define SRST_T_WDT_S 294933
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define SRST_P_I2C0 294934
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define SRST_I2C0 294935
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define SRST_P_I2C2 294938
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define SRST_I2C2 294939
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define SRST_P_I2C3 294940
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define SRST_I2C3 294941
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define SRST_P_I2C4 294942
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define SRST_I2C4 294943
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /********Name=PERISOFTRST_CON02,Offset=0x12A08********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define SRST_P_GPIO4 294944
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define SRST_GPIO4 294945
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define SRST_P_PERI_IOC 294946
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define SRST_P_UART2 294947
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define SRST_S_UART2 294950
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define SRST_P_UART3 294951
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define SRST_S_UART3 294954
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define SRST_P_UART4 294955
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define SRST_S_UART4 294958
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define SRST_P_UART5 294959
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /********Name=PERISOFTRST_CON03,Offset=0x12A0C********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define SRST_S_UART5 294962
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define SRST_P_SARADC 294963
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define SRST_SARADC 294964
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define SRST_SARADC_PHY 294965
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define SRST_P_SPI1 294966
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define SRST_SPI1 294967
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define SRST_H_TRNG_NS 294969
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define SRST_H_TRNG_S 294970
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define SRST_CORE_CRYPTO 294971
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define SRST_PKA_CRYPTO 294972
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define SRST_A_CRYPTO 294973
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define SRST_H_CRYPTO 294974
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define SRST_P_PWM1_PERI 294975
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /********Name=PERISOFTRST_CON04,Offset=0x12A10********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define SRST_PWM1_PERI 294976
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define SRST_P_PWM2_PERI 294978
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define SRST_PWM2_PERI 294979
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define SRST_P_PERI_GRF 294981
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define SRST_P_PERI_CRU 294982
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define SRST_A_USBOTG 294983
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define SRST_A_BUS_BIU 294986
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define SRST_H_EMMC 294989
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define SRST_H_SFC 294990
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /********Name=PERISOFTRST_CON05,Offset=0x12A14********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define SRST_S_SFC 294992
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define SRST_P_USBPHY 294993
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define SRST_USBPHY_POR 294994
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define SRST_USBPHY_OTG 294995
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define SRST_A_DMAC 295000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define SRST_A_DECOM 295001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define SRST_P_DECOM 295002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define SRST_D_DECOM 295003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define SRST_P_PERI_SGRF 295004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define SRST_H_SAI 295005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define SRST_M_SAI 295006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define SRST_M_I2S0_8CH_TX 295007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /********Name=PERISOFTRST_CON06,Offset=0x12A18********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define SRST_H_I2S0 295008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define SRST_M_DSM 295009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define SRST_P_DSM 295010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define SRST_P_ACODEC 295011
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define SRST_M_I2S0_8CH_RX 295014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define SRST_P_DFT2APB 295015
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define SRST_H_IVE 295017
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define SRST_A_IVE 295018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define SRST_P_UART0 295019
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define SRST_S_UART0 295022
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define SRST_P_UART1 295023
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /********Name=PERISOFTRST_CON07,Offset=0x12A1C********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define SRST_S_UART1 295026
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define SRST_P_PWM0_PERI 295027
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define SRST_PWM0_PERI 295028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /********Name=VISOFTRST_CON00,Offset=0x14A00********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define SRST_H_VI_BIU 327684
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define SRST_A_VI_BIU 327685
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define SRST_P_VI_BIU 327686
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define SRST_CORE_ISP3P2 327689
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define SRST_D_VICAP 327690
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define SRST_P_VICAP 327691
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define SRST_A_VICAP 327692
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define SRST_H_VICAP 327693
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define SRST_VICAP_I0 327694
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define SRST_VICAP_I1 327695
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /********Name=VISOFTRST_CON01,Offset=0x14A04********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define SRST_VICAP_RX0 327696
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define SRST_VICAP_RX1 327697
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define SRST_VICAP_ISP0 327698
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define SRST_P_CSIHOST0 327700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define SRST_P_CSIHOST1 327702
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define SRST_H_SDMMC 327708
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define SRST_SDMMC_DETN_FLT 327709
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define SRST_P_MIPICSIPHY 327710
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define SRST_P_GPIO3 327711
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /********Name=VISOFTRST_CON02,Offset=0x14A08********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define SRST_GPIO3 327712
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define SRST_P_VI_IOC 327713
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define SRST_P_VI_GRF 327714
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define SRST_P_VI_SGRF 327715
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define SRST_P_VI_CRU 327716
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define SRST_P_VI_RTC_TEST 327717
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define SRST_P_VI_RTC_NIU 327719
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) /********Name=NPUSOFTRST_CON00,Offset=0x16A00********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define SRST_H_NPU_BIU 360451
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define SRST_A_NPU_BIU 360452
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define SRST_P_NPU_BIU 360453
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define SRST_P_NPU_CRU 360454
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define SRST_P_NPU_SGRF 360455
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define SRST_P_NPU_GRF 360456
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define SRST_H_RKNN 360457
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define SRST_A_RKNN 360458
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) /********Name=CORESOFTRST_CON00,Offset=0x18A00********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define SRST_NCOREPORESET 393217
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define SRST_NCORESET 393218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define SRST_NDBGRESET 393219
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define SRST_NL2RESET 393220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define SRST_A_M_CORE_BIU 393221
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define SRST_P_DBG 393222
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define SRST_POT_DBG 393223
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define SRST_NT_DBG 393224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define SRST_P_CORE_GRF 393227
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define SRST_H_CPU_BIU 393228
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define SRST_P_CPU_BIU 393229
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define SRST_PVTM_CORE 393230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define SRST_P_PVTM_CORE 393231
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) /********Name=CORESOFTRST_CON01,Offset=0x18A04********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define SRST_REF_PVTPLL_CORE 393232
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define SRST_CORE_MCU 393233
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define SRST_CORE_MCU_PWRUP 393234
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define SRST_CORE_MCU_CPU 393235
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define SRST_T_CORE_MCU_CPU 393236
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define SRST_MCU_BIU 393237
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define SRST_P_MAILBOX 393240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define SRST_P_INTMUX 393241
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define SRST_P_CORE_CRU 393242
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define SRST_P_CORE_SGRF 393243
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define SRST_H_CACHE 393244
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) /********Name=VEPUSOFTRST_CON00,Offset=0x1AA00********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define SRST_H_VEPU_BIU 425988
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define SRST_A_VEPU_BIU 425989
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define SRST_A_VEPU_COM_BIU 425990
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define SRST_P_VEPU_BIU 425991
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define SRST_H_VEPU 425992
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define SRST_A_VEPU 425993
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define SRST_CORE_VEPU 425994
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define SRST_H_VEPU_PP 425995
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define SRST_A_VEPU_PP 425996
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define SRST_CORE_VEPU_DVBM 425997
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define SRST_P_VICAP_VEPU 425998
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define SRST_P_GPIO1 425999
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) /********Name=VEPUSOFTRST_CON01,Offset=0x1AA04********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define SRST_GPIO1 426000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define SRST_P_VEPU_IOC 426001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define SRST_P_SPI0 426002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define SRST_SPI0 426003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define SRST_P_VEPU_CRU 426005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define SRST_P_VEPU_SGRF 426006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define SRST_P_VEPU_GRF 426007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define SRST_UART_DETN_FLT 426008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) /********Name=VOSOFTRST_CON00,Offset=0x1CA00********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define SRST_A_VO_BIU 458755
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define SRST_H_VO_BIU 458756
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define SRST_H_RGA2E 458759
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define SRST_A_RGA2E 458760
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define SRST_CORE_RGA2E 458761
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define SRST_P_VO_GRF 458762
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define SRST_A_VOP_BIU 458764
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define SRST_H_VOP 458765
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define SRST_D_VOP 458766
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define SRST_A_VOP 458767
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /********Name=VOSOFTRST_CON01,Offset=0x1CA04********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define SRST_P_MAC_BIU 458774
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define SRST_A_MAC_BIU 458775
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define SRST_A_MAC 458776
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define SRST_P_VO_SGRF 458780
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define SRST_P_VO_CRU 458781
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define SRST_H_SDIO 458783
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) /********Name=VOSOFTRST_CON02,Offset=0x1CA08********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define SRST_P_TSADC 458784
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #define SRST_TSADC 458785
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define SRST_P_OTPC_NS 458787
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define SRST_SBPI_OTPC_NS 458789
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define SRST_USER_OTPC_NS 458790
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define SRST_P_OTPC_S 458791
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define SRST_SBPI_OTPC_S 458793
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define SRST_USER_OTPC_S 458794
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define SRST_OTPC_ARB 458795
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define SRST_MACPHY 458797
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define SRST_P_OTP_MASK 458798
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define SRST_PMC_OTP 458799
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) /********Name=VOSOFTRST_CON03,Offset=0x1CA0C********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define SRST_P_GPIO2 458800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define SRST_GPIO2 458801
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define SRST_P_VO_IOC 458802
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) /********Name=DDRSOFTRST_CON00,Offset=0x1EA00********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define SRST_P_DDR_BIU 491522
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define SRST_P_DDRC 491525
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define SRST_P_DDRMON 491527
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define SRST_TIMER_DDRMON 491528
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define SRST_P_DFICTRL 491531
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define SRST_A_SYS_SHRM 491533
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define SRST_A_SHRM_NIU 491534
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define SRST_P_DDR_GRF 491535
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) /********Name=DDRSOFTRST_CON01,Offset=0x1EA04********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define SRST_P_DDR_CRU 491536
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #define SRST_P_DDR_HWLP 491538
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #define SRST_P_DDRPHY 491539
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) /********Name=SUBDDRSOFTRST_CON00,Offset=0x1FA00********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define SRST_MSCH_BIU 507904
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #define SRST_A_DDRC 507905
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #define SRST_CORE_DDRC 507907
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define SRST_DDRMON 507908
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define SRST_DFICTRL 507909
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define SRST_DDR_PHY 507910
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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