Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (C) 2017 ROCKCHIP, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * This software is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * License version 2, as published by the Free Software Foundation, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * may be copied, distributed, and modified under those terms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  * This program is distributed in the hope that it will be useful,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  * but WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #ifndef _DT_BINDINGS_CLOCK_ROCKCHIP_DDR_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define _DT_BINDINGS_CLOCK_ROCKCHIP_DDR_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define DDR2_DEFAULT	(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define DDR3_800D	(0)	/* 5-5-5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define DDR3_800E	(1)	/* 6-6-6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define DDR3_1066E	(2)	/* 6-6-6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define DDR3_1066F	(3)	/* 7-7-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define DDR3_1066G	(4)	/* 8-8-8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DDR3_1333F	(5)	/* 7-7-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DDR3_1333G	(6)	/* 8-8-8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define DDR3_1333H	(7)	/* 9-9-9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DDR3_1333J	(8)	/* 10-10-10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DDR3_1600G	(9)	/* 8-8-8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define DDR3_1600H	(10)	/* 9-9-9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define DDR3_1600J	(11)	/* 10-10-10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DDR3_1600K	(12)	/* 11-11-11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DDR3_1866J	(13)	/* 10-10-10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DDR3_1866K	(14)	/* 11-11-11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DDR3_1866L	(15)	/* 12-12-12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DDR3_1866M	(16)	/* 13-13-13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DDR3_2133K	(17)	/* 11-11-11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DDR3_2133L	(18)	/* 12-12-12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DDR3_2133M	(19)	/* 13-13-13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DDR3_2133N	(20)	/* 14-14-14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DDR3_DEFAULT	(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DDR_DDR2	(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define DDR_LPDDR	(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define DDR_LPDDR2	(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define DDR4_1600J	(0)	/* 10-10-10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define DDR4_1600K	(1)	/* 11-11-11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define DDR4_1600L	(2)	/* 12-12-12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define DDR4_1866L	(3)	/* 12-12-12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define DDR4_1866M	(4)	/* 13-13-13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define DDR4_1866N	(5)	/* 14-14-14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define DDR4_2133N	(6)	/* 14-14-14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define DDR4_2133P	(7)	/* 15-15-15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define DDR4_2133R	(8)	/* 16-16-16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define DDR4_2400P	(9)	/* 15-15-15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define DDR4_2400R	(10)	/* 16-16-16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define DDR4_2400U	(11)	/* 18-18-18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define DDR4_DEFAULT	(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define PAUSE_CPU_STACK_SIZE	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #endif