^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2020 Rockchip Electronics Co. Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Wyon Bi <bivvy.bi@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef _RK628_CGU_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define _RK628_CGU_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define CGU_CLK_CPLL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define CGU_CLK_GPLL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define CGU_CLK_CPLL_MUX 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define CGU_CLK_GPLL_MUX 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define CGU_PCLK_GPIO0 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define CGU_PCLK_GPIO1 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define CGU_PCLK_GPIO2 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CGU_PCLK_GPIO3 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CGU_PCLK_TXPHY_CON 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CGU_PCLK_EFUSE 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CGU_PCLK_DSI0 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CGU_PCLK_DSI1 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CGU_PCLK_CSI 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CGU_PCLK_HDMITX 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CGU_PCLK_RXPHY 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CGU_PCLK_HDMIRX 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CGU_PCLK_DPRX 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CGU_PCLK_GVIHOST 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CGU_CLK_CFG_DPHY0 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CGU_CLK_CFG_DPHY1 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CGU_CLK_TXESC 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CGU_CLK_DPRX_VID 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CGU_CLK_IMODET 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CGU_CLK_HDMIRX_AUD 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CGU_CLK_HDMIRX_CEC 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CGU_CLK_RX_READ 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CGU_SCLK_VOP 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CGU_PCLK_LOGIC 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CGU_CLK_GPIO_DB0 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CGU_CLK_GPIO_DB1 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CGU_CLK_GPIO_DB2 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CGU_CLK_GPIO_DB3 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CGU_CLK_I2S_8CH_SRC 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CGU_CLK_I2S_8CH_FRAC 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CGU_MCLK_I2S_8CH 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CGU_I2S_MCLKOUT 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CGU_BT1120DEC 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CGU_CLK_TESTOUT 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CGU_NR_CLKS 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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