^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Elaine Zhang <zhangqing@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3588_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define _DT_BINDINGS_CLK_ROCKCHIP_RK3588_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /* cru-clocks indices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /* cru plls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define PLL_B0PLL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define PLL_B1PLL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define PLL_LPLL 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define PLL_V0PLL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define PLL_AUPLL 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PLL_CPLL 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PLL_GPLL 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PLL_NPLL 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PLL_PPLL 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define ARMCLK_L 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define ARMCLK_B01 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define ARMCLK_B23 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* cru clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PCLK_BIGCORE0_ROOT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PCLK_BIGCORE0_PVTM 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PCLK_BIGCORE1_ROOT 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PCLK_BIGCORE1_PVTM 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PCLK_DSU_S_ROOT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PCLK_DSU_ROOT 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PCLK_DSU_NS_ROOT 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PCLK_LITCORE_PVTM 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PCLK_DBG 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PCLK_DSU 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PCLK_S_DAPLITE 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PCLK_M_DAPLITE 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MBIST_MCLK_PDM1 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MBIST_CLK_ACDCDIG 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define HCLK_I2S2_2CH 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define HCLK_I2S3_2CH 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CLK_I2S2_2CH_SRC 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CLK_I2S2_2CH_FRAC 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CLK_I2S2_2CH 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MCLK_I2S2_2CH 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define I2S2_2CH_MCLKOUT 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CLK_DAC_ACDCDIG 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CLK_I2S3_2CH_SRC 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CLK_I2S3_2CH_FRAC 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CLK_I2S3_2CH 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MCLK_I2S3_2CH 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define I2S3_2CH_MCLKOUT 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PCLK_ACDCDIG 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define HCLK_I2S0_8CH 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CLK_I2S0_8CH_TX_SRC 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CLK_I2S0_8CH_TX_FRAC 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MCLK_I2S0_8CH_TX 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CLK_I2S0_8CH_TX 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CLK_I2S0_8CH_RX_SRC 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CLK_I2S0_8CH_RX_FRAC 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MCLK_I2S0_8CH_RX 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CLK_I2S0_8CH_RX 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define I2S0_8CH_MCLKOUT 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define HCLK_PDM1 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MCLK_PDM1 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define HCLK_AUDIO_ROOT 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PCLK_AUDIO_ROOT 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define HCLK_SPDIF0 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define CLK_SPDIF0_SRC 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define CLK_SPDIF0_FRAC 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define MCLK_SPDIF0 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define CLK_SPDIF0 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define CLK_SPDIF1 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define HCLK_SPDIF1 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define CLK_SPDIF1_SRC 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define CLK_SPDIF1_FRAC 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define MCLK_SPDIF1 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define ACLK_AV1_ROOT 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define ACLK_AV1 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define PCLK_AV1_ROOT 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define PCLK_AV1 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define PCLK_MAILBOX0 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define PCLK_MAILBOX1 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define PCLK_MAILBOX2 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define PCLK_PMU2 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define PCLK_PMUCM0_INTMUX 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define PCLK_DDRCM0_INTMUX 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define PCLK_TOP 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define PCLK_PWM1 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define CLK_PWM1 84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define CLK_PWM1_CAPTURE 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define PCLK_PWM2 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define CLK_PWM2 87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define CLK_PWM2_CAPTURE 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define PCLK_PWM3 89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define CLK_PWM3 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define CLK_PWM3_CAPTURE 91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define PCLK_BUSTIMER0 92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define PCLK_BUSTIMER1 93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define CLK_BUS_TIMER_ROOT 94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define CLK_BUSTIMER0 95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define CLK_BUSTIMER1 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define CLK_BUSTIMER2 97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define CLK_BUSTIMER3 98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define CLK_BUSTIMER4 99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define CLK_BUSTIMER5 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define CLK_BUSTIMER6 101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define CLK_BUSTIMER7 102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define CLK_BUSTIMER8 103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define CLK_BUSTIMER9 104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define CLK_BUSTIMER10 105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define CLK_BUSTIMER11 106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define PCLK_WDT0 107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define TCLK_WDT0 108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define PCLK_CAN0 111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define CLK_CAN0 112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define PCLK_CAN1 113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define CLK_CAN1 114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define PCLK_CAN2 115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define CLK_CAN2 116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define ACLK_DECOM 117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define PCLK_DECOM 118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define DCLK_DECOM 119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define ACLK_DMAC0 120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define ACLK_DMAC1 121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define ACLK_DMAC2 122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define ACLK_BUS_ROOT 123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define ACLK_GIC 124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define PCLK_GPIO1 125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define DBCLK_GPIO1 126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define PCLK_GPIO2 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define DBCLK_GPIO2 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define PCLK_GPIO3 129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define DBCLK_GPIO3 130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define PCLK_GPIO4 131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define DBCLK_GPIO4 132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define PCLK_I2C1 133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define PCLK_I2C2 134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define PCLK_I2C3 135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define PCLK_I2C4 136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define PCLK_I2C5 137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define PCLK_I2C6 138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define PCLK_I2C7 139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define PCLK_I2C8 140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define CLK_I2C1 141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define CLK_I2C2 142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define CLK_I2C3 143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define CLK_I2C4 144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define CLK_I2C5 145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define CLK_I2C6 146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define CLK_I2C7 147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define CLK_I2C8 148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define PCLK_OTPC_NS 149
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define CLK_OTPC_NS 150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define CLK_OTPC_ARB 151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define CLK_OTPC_AUTO_RD_G 152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define CLK_OTP_PHY_G 153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define PCLK_SARADC 156
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define CLK_SARADC 157
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define PCLK_SPI0 158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define PCLK_SPI1 159
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define PCLK_SPI2 160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define PCLK_SPI3 161
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define PCLK_SPI4 162
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define CLK_SPI0 163
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define CLK_SPI1 164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define CLK_SPI2 165
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define CLK_SPI3 166
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define CLK_SPI4 167
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define ACLK_SPINLOCK 168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define PCLK_TSADC 169
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define CLK_TSADC 170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define PCLK_UART1 171
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define PCLK_UART2 172
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define PCLK_UART3 173
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define PCLK_UART4 174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define PCLK_UART5 175
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define PCLK_UART6 176
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define PCLK_UART7 177
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define PCLK_UART8 178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define PCLK_UART9 179
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define CLK_UART1_SRC 180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define CLK_UART1_FRAC 181
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define CLK_UART1 182
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define SCLK_UART1 183
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define CLK_UART2_SRC 184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define CLK_UART2_FRAC 185
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define CLK_UART2 186
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define SCLK_UART2 187
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define CLK_UART3_SRC 188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define CLK_UART3_FRAC 189
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define CLK_UART3 190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define SCLK_UART3 191
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define CLK_UART4_SRC 192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define CLK_UART4_FRAC 193
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define CLK_UART4 194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define SCLK_UART4 195
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define CLK_UART5_SRC 196
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define CLK_UART5_FRAC 197
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define CLK_UART5 198
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define SCLK_UART5 199
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define CLK_UART6_SRC 200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define CLK_UART6_FRAC 201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define CLK_UART6 202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define SCLK_UART6 203
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define CLK_UART7_SRC 204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define CLK_UART7_FRAC 205
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define CLK_UART7 206
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define SCLK_UART7 207
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define CLK_UART8_SRC 208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define CLK_UART8_FRAC 209
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define CLK_UART8 210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define SCLK_UART8 211
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define CLK_UART9_SRC 212
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define CLK_UART9_FRAC 213
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define CLK_UART9 214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define SCLK_UART9 215
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define ACLK_CENTER_ROOT 216
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define ACLK_CENTER_LOW_ROOT 217
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define HCLK_CENTER_ROOT 218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define PCLK_CENTER_ROOT 219
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define ACLK_DMA2DDR 220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define ACLK_DDR_SHAREMEM 221
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define ACLK_CENTER_S200_ROOT 222
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define ACLK_CENTER_S400_ROOT 223
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define FCLK_DDR_CM0_CORE 224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define CLK_DDR_TIMER_ROOT 225
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define CLK_DDR_TIMER0 226
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define CLK_DDR_TIMER1 227
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define TCLK_WDT_DDR 228
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define CLK_DDR_CM0_RTC 228
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define PCLK_WDT 230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define PCLK_TIMER 231
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define PCLK_DMA2DDR 232
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define PCLK_SHAREMEM 233
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define CLK_50M_SRC 234
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define CLK_100M_SRC 235
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define CLK_150M_SRC 236
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define CLK_200M_SRC 237
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define CLK_250M_SRC 238
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define CLK_300M_SRC 239
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define CLK_350M_SRC 240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define CLK_400M_SRC 241
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define CLK_450M_SRC 242
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define CLK_500M_SRC 243
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define CLK_600M_SRC 244
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define CLK_650M_SRC 245
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define CLK_700M_SRC 246
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define CLK_800M_SRC 247
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define CLK_1000M_SRC 248
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define CLK_1200M_SRC 249
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define ACLK_TOP_M300_ROOT 250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define ACLK_TOP_M500_ROOT 251
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define ACLK_TOP_M400_ROOT 252
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define ACLK_TOP_S200_ROOT 253
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define ACLK_TOP_S400_ROOT 254
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define CLK_MIPI_CAMARAOUT_M0 255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define CLK_MIPI_CAMARAOUT_M1 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define CLK_MIPI_CAMARAOUT_M2 257
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define CLK_MIPI_CAMARAOUT_M3 258
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define CLK_MIPI_CAMARAOUT_M4 259
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define MCLK_GMAC0_OUT 260
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define REFCLKO25M_ETH0_OUT 261
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define REFCLKO25M_ETH1_OUT 262
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define CLK_CIFOUT_OUT 263
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define PCLK_MIPI_DCPHY0 264
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define PCLK_MIPI_DCPHY1 265
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define PCLK_CSIPHY0 268
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define PCLK_CSIPHY1 269
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define ACLK_TOP_ROOT 270
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define PCLK_TOP_ROOT 271
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define ACLK_LOW_TOP_ROOT 272
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define PCLK_CRU 273
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define PCLK_GPU_ROOT 274
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define CLK_GPU_SRC 275
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define CLK_GPU 276
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define CLK_GPU_COREGROUP 277
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define CLK_GPU_STACKS 278
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define PCLK_GPU_PVTM 279
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define CLK_GPU_PVTM 280
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define CLK_CORE_GPU_PVTM 281
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define PCLK_GPU_GRF 282
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define ACLK_ISP1_ROOT 283
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define HCLK_ISP1_ROOT 284
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define CLK_ISP1_CORE 285
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define CLK_ISP1_CORE_MARVIN 286
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define CLK_ISP1_CORE_VICAP 287
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define ACLK_ISP1 288
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define HCLK_ISP1 289
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define ACLK_NPU1 290
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define HCLK_NPU1 291
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define ACLK_NPU2 292
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define HCLK_NPU2 293
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define HCLK_NPU_CM0_ROOT 294
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define FCLK_NPU_CM0_CORE 295
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define CLK_NPU_CM0_RTC 296
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define PCLK_NPU_PVTM 297
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define PCLK_NPU_GRF 298
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define CLK_NPU_PVTM 299
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define CLK_CORE_NPU_PVTM 300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define ACLK_NPU0 301
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define HCLK_NPU0 302
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define HCLK_NPU_ROOT 303
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define CLK_NPU_DSU0 304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define PCLK_NPU_ROOT 305
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define PCLK_NPU_TIMER 306
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define CLK_NPUTIMER_ROOT 307
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define CLK_NPUTIMER0 308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define CLK_NPUTIMER1 309
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define PCLK_NPU_WDT 310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define TCLK_NPU_WDT 311
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define HCLK_EMMC 312
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define ACLK_EMMC 313
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define CCLK_EMMC 314
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define BCLK_EMMC 315
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define TMCLK_EMMC 316
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define SCLK_SFC 317
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define HCLK_SFC 318
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define HCLK_SFC_XIP 319
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define HCLK_NVM_ROOT 320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define ACLK_NVM_ROOT 321
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define CLK_GMAC0_PTP_REF 322
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define CLK_GMAC1_PTP_REF 323
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define CLK_GMAC_125M 324
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define CLK_GMAC_50M 325
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define ACLK_PHP_GIC_ITS 326
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define ACLK_MMU_PCIE 327
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define ACLK_MMU_PHP 328
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define ACLK_PCIE_4L_DBI 329
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define ACLK_PCIE_2L_DBI 330
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define ACLK_PCIE_1L0_DBI 331
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define ACLK_PCIE_1L1_DBI 332
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define ACLK_PCIE_1L2_DBI 333
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define ACLK_PCIE_4L_MSTR 334
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define ACLK_PCIE_2L_MSTR 335
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define ACLK_PCIE_1L0_MSTR 336
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define ACLK_PCIE_1L1_MSTR 337
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define ACLK_PCIE_1L2_MSTR 338
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define ACLK_PCIE_4L_SLV 339
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define ACLK_PCIE_2L_SLV 340
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define ACLK_PCIE_1L0_SLV 341
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define ACLK_PCIE_1L1_SLV 342
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define ACLK_PCIE_1L2_SLV 343
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define PCLK_PCIE_4L 344
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define PCLK_PCIE_2L 345
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define PCLK_PCIE_1L0 347
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define PCLK_PCIE_1L1 348
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define PCLK_PCIE_1L2 349
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define CLK_PCIE_AUX0 350
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define CLK_PCIE_AUX1 351
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define CLK_PCIE_AUX2 352
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define CLK_PCIE_AUX3 353
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define CLK_PCIE_AUX4 354
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define CLK_PIPEPHY0_REF 355
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define CLK_PIPEPHY1_REF 356
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define CLK_PIPEPHY2_REF 357
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define PCLK_PHP_ROOT 358
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define PCLK_GMAC0 359
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define PCLK_GMAC1 360
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define ACLK_PCIE_ROOT 361
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define ACLK_PHP_ROOT 362
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define ACLK_PCIE_BRIDGE 363
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define ACLK_GMAC0 364
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define ACLK_GMAC1 365
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define CLK_PMALIVE0 366
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define CLK_PMALIVE1 367
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define CLK_PMALIVE2 368
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define ACLK_SATA0 369
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define ACLK_SATA1 370
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define ACLK_SATA2 371
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define CLK_RXOOB0 372
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define CLK_RXOOB1 373
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define CLK_RXOOB2 374
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define ACLK_USB3OTG2 375
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define SUSPEND_CLK_USB3OTG2 376
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define REF_CLK_USB3OTG2 377
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define CLK_UTMI_OTG2 378
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define CLK_PIPEPHY0_PIPE_G 379
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define CLK_PIPEPHY1_PIPE_G 380
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define CLK_PIPEPHY2_PIPE_G 381
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define CLK_PIPEPHY0_PIPE_ASIC_G 382
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define CLK_PIPEPHY1_PIPE_ASIC_G 383
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define CLK_PIPEPHY2_PIPE_ASIC_G 384
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define CLK_PIPEPHY2_PIPE_U3_G 385
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define CLK_PCIE1L2_PIPE 386
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define CLK_PCIE4L_PIPE 387
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define CLK_PCIE2L_PIPE 388
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define PCLK_PCIE_COMBO_PIPE_PHY0 389
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define PCLK_PCIE_COMBO_PIPE_PHY1 390
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define PCLK_PCIE_COMBO_PIPE_PHY2 391
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define PCLK_PCIE_COMBO_PIPE_PHY 392
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define HCLK_RGA3_1 393
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define ACLK_RGA3_1 394
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define CLK_RGA3_1_CORE 395
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define ACLK_RGA3_ROOT 396
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define HCLK_RGA3_ROOT 397
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define ACLK_RKVDEC_CCU 398
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define HCLK_RKVDEC0 399
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define ACLK_RKVDEC0 400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define CLK_RKVDEC0_CA 401
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define CLK_RKVDEC0_HEVC_CA 402
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define CLK_RKVDEC0_CORE 403
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define HCLK_RKVDEC1 404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define ACLK_RKVDEC1 405
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define CLK_RKVDEC1_CA 406
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define CLK_RKVDEC1_HEVC_CA 407
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define CLK_RKVDEC1_CORE 408
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define HCLK_SDIO 409
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define CCLK_SRC_SDIO 410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define ACLK_USB_ROOT 411
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define HCLK_USB_ROOT 412
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define HCLK_HOST0 413
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define HCLK_HOST_ARB0 414
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define HCLK_HOST1 415
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define HCLK_HOST_ARB1 416
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define ACLK_USB3OTG0 417
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define SUSPEND_CLK_USB3OTG0 418
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define REF_CLK_USB3OTG0 419
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define ACLK_USB3OTG1 420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define SUSPEND_CLK_USB3OTG1 421
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define REF_CLK_USB3OTG1 422
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define UTMI_OHCI_CLK48_HOST0 423
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define UTMI_OHCI_CLK48_HOST1 424
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define HCLK_IEP2P0 425
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define ACLK_IEP2P0 426
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define CLK_IEP2P0_CORE 427
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define ACLK_JPEG_ENCODER0 428
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define HCLK_JPEG_ENCODER0 429
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define ACLK_JPEG_ENCODER1 430
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define HCLK_JPEG_ENCODER1 431
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define ACLK_JPEG_ENCODER2 432
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define HCLK_JPEG_ENCODER2 433
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define ACLK_JPEG_ENCODER3 434
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define HCLK_JPEG_ENCODER3 435
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define ACLK_JPEG_DECODER 436
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define HCLK_JPEG_DECODER 437
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define HCLK_RGA2 438
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define ACLK_RGA2 439
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define CLK_RGA2_CORE 440
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define HCLK_RGA3_0 441
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define ACLK_RGA3_0 442
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define CLK_RGA3_0_CORE 443
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define ACLK_VDPU_ROOT 444
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define ACLK_VDPU_LOW_ROOT 445
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define HCLK_VDPU_ROOT 446
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define ACLK_JPEG_DECODER_ROOT 447
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define ACLK_VPU 448
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define HCLK_VPU 449
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define HCLK_RKVENC0_ROOT 450
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define ACLK_RKVENC0_ROOT 451
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define HCLK_RKVENC0 452
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define ACLK_RKVENC0 453
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define CLK_RKVENC0_CORE 454
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define HCLK_RKVENC1_ROOT 455
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define ACLK_RKVENC1_ROOT 456
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define HCLK_RKVENC1 457
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define ACLK_RKVENC1 458
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define CLK_RKVENC1_CORE 459
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define ICLK_CSIHOST01 460
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define ICLK_CSIHOST0 461
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define ICLK_CSIHOST1 462
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define PCLK_CSI_HOST_0 463
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define PCLK_CSI_HOST_1 464
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define PCLK_CSI_HOST_2 465
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define PCLK_CSI_HOST_3 466
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define PCLK_CSI_HOST_4 467
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define PCLK_CSI_HOST_5 468
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define ACLK_FISHEYE0 469
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define HCLK_FISHEYE0 470
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define CLK_FISHEYE0_CORE 471
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define ACLK_FISHEYE1 472
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define HCLK_FISHEYE1 473
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define CLK_FISHEYE1_CORE 474
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define CLK_ISP0_CORE 475
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define CLK_ISP0_CORE_MARVIN 476
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define CLK_ISP0_CORE_VICAP 477
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define ACLK_ISP0 478
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define HCLK_ISP0 479
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define ACLK_VI_ROOT 480
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define HCLK_VI_ROOT 481
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define PCLK_VI_ROOT 482
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define DCLK_VICAP 483
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define ACLK_VICAP 484
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define HCLK_VICAP 485
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define PCLK_DP0 486
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define PCLK_DP1 487
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define PCLK_S_DP0 488
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define PCLK_S_DP1 489
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define CLK_DP0 490
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define CLK_DP1 491
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define HCLK_HDCP_KEY0 492
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define ACLK_HDCP0 493
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define HCLK_HDCP0 494
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define PCLK_HDCP0 495
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define HCLK_I2S4_8CH 496
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define ACLK_TRNG0 497
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define PCLK_TRNG0 498
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define ACLK_VO0_ROOT 499
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define HCLK_VO0_ROOT 500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define HCLK_VO0_S_ROOT 501
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define PCLK_VO0_ROOT 502
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define PCLK_VO0_S_ROOT 503
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define PCLK_VO0GRF 504
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define CLK_I2S4_8CH_TX_SRC 505
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define CLK_I2S4_8CH_TX_FRAC 506
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define MCLK_I2S4_8CH_TX 507
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define CLK_I2S4_8CH_TX 508
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define HCLK_I2S8_8CH 510
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define CLK_I2S8_8CH_TX_SRC 511
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define CLK_I2S8_8CH_TX_FRAC 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define MCLK_I2S8_8CH_TX 513
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define CLK_I2S8_8CH_TX 514
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define HCLK_SPDIF2_DP0 516
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define CLK_SPDIF2_DP0_SRC 517
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define CLK_SPDIF2_DP0_FRAC 518
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define MCLK_SPDIF2_DP0 519
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define CLK_SPDIF2_DP0 520
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define MCLK_SPDIF2 521
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define HCLK_SPDIF5_DP1 522
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define CLK_SPDIF5_DP1_SRC 523
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define CLK_SPDIF5_DP1_FRAC 524
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define MCLK_SPDIF5_DP1 525
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define CLK_SPDIF5_DP1 526
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define MCLK_SPDIF5 527
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define PCLK_EDP0 528
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define CLK_EDP0_24M 529
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define CLK_EDP0_200M 530
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define PCLK_EDP1 531
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define CLK_EDP1_24M 532
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define CLK_EDP1_200M 533
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define HCLK_HDCP_KEY1 534
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define ACLK_HDCP1 535
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define HCLK_HDCP1 536
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #define PCLK_HDCP1 537
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define ACLK_HDMIRX 538
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define PCLK_HDMIRX 539
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define CLK_HDMIRX_REF 540
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define CLK_HDMIRX_AUD_SRC 541
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define CLK_HDMIRX_AUD_FRAC 542
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define CLK_HDMIRX_AUD 543
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define CLK_HDMIRX_AUD_P_MUX 544
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define PCLK_HDMITX0 545
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define CLK_HDMITX0_EARC 546
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define CLK_HDMITX0_REF 547
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define PCLK_HDMITX1 548
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define CLK_HDMITX1_EARC 549
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define CLK_HDMITX1_REF 550
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define CLK_HDMITRX_REFSRC 551
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define ACLK_TRNG1 552
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define PCLK_TRNG1 553
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define ACLK_HDCP1_ROOT 554
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define ACLK_HDMIRX_ROOT 555
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define HCLK_VO1_ROOT 556
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define HCLK_VO1_S_ROOT 557
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define PCLK_VO1_ROOT 558
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define PCLK_VO1_S_ROOT 559
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define PCLK_S_EDP0 560
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define PCLK_S_EDP1 561
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define PCLK_S_HDMIRX 562
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #define HCLK_I2S10_8CH 563
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #define CLK_I2S10_8CH_RX_SRC 564
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #define CLK_I2S10_8CH_RX_FRAC 565
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define CLK_I2S10_8CH_RX 566
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #define MCLK_I2S10_8CH_RX 567
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #define HCLK_I2S7_8CH 568
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define CLK_I2S7_8CH_RX_SRC 569
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define CLK_I2S7_8CH_RX_FRAC 570
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define CLK_I2S7_8CH_RX 571
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #define MCLK_I2S7_8CH_RX 572
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #define HCLK_I2S9_8CH 574
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #define CLK_I2S9_8CH_RX_SRC 575
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #define CLK_I2S9_8CH_RX_FRAC 576
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define CLK_I2S9_8CH_RX 577
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #define MCLK_I2S9_8CH_RX 578
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define CLK_I2S5_8CH_TX_SRC 579
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define CLK_I2S5_8CH_TX_FRAC 580
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define CLK_I2S5_8CH_TX 581
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define MCLK_I2S5_8CH_TX 582
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #define HCLK_I2S5_8CH 584
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define CLK_I2S6_8CH_TX_SRC 585
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define CLK_I2S6_8CH_TX_FRAC 586
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #define CLK_I2S6_8CH_TX 587
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #define MCLK_I2S6_8CH_TX 588
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #define CLK_I2S6_8CH_RX_SRC 589
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define CLK_I2S6_8CH_RX_FRAC 590
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) #define CLK_I2S6_8CH_RX 591
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #define MCLK_I2S6_8CH_RX 592
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #define I2S6_8CH_MCLKOUT 593
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #define HCLK_I2S6_8CH 594
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) #define HCLK_SPDIF3 595
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #define CLK_SPDIF3_SRC 596
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #define CLK_SPDIF3_FRAC 597
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #define CLK_SPDIF3 598
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #define MCLK_SPDIF3 599
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #define HCLK_SPDIF4 600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) #define CLK_SPDIF4_SRC 601
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) #define CLK_SPDIF4_FRAC 602
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #define CLK_SPDIF4 603
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #define MCLK_SPDIF4 604
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) #define HCLK_SPDIFRX0 605
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #define MCLK_SPDIFRX0 606
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) #define HCLK_SPDIFRX1 607
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #define MCLK_SPDIFRX1 608
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) #define HCLK_SPDIFRX2 609
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #define MCLK_SPDIFRX2 610
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #define ACLK_VO1USB_TOP_ROOT 611
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #define HCLK_VO1USB_TOP_ROOT 612
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #define CLK_HDMIHDP0 613
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) #define CLK_HDMIHDP1 614
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #define PCLK_HDPTX0 615
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #define PCLK_HDPTX1 616
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #define PCLK_USBDPPHY0 617
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #define PCLK_USBDPPHY1 618
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #define ACLK_VOP_ROOT 619
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #define ACLK_VOP_LOW_ROOT 620
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #define HCLK_VOP_ROOT 621
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #define PCLK_VOP_ROOT 622
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) #define HCLK_VOP 623
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) #define ACLK_VOP 624
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) #define DCLK_VOP0_SRC 625
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #define DCLK_VOP1_SRC 626
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) #define DCLK_VOP2_SRC 627
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) #define DCLK_VOP0 628
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #define DCLK_VOP1 629
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #define DCLK_VOP2 630
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) #define DCLK_VOP3 631
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) #define PCLK_DSIHOST0 632
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) #define PCLK_DSIHOST1 633
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) #define CLK_DSIHOST0 634
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #define CLK_DSIHOST1 635
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) #define CLK_VOP_PMU 636
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) #define ACLK_VOP_DOBY 637
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) #define ACLK_VOP_DIV2_SRC 638
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) #define CLK_USBDP_PHY0_IMMORTAL 639
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) #define CLK_USBDP_PHY1_IMMORTAL 640
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) #define CLK_PMU0 641
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) #define PCLK_PMU0 642
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) #define PCLK_PMU0IOC 643
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) #define PCLK_GPIO0 644
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) #define DBCLK_GPIO0 645
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) #define PCLK_I2C0 646
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) #define CLK_I2C0 647
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) #define HCLK_I2S1_8CH 648
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) #define CLK_I2S1_8CH_TX_SRC 649
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) #define CLK_I2S1_8CH_TX_FRAC 650
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) #define CLK_I2S1_8CH_TX 651
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) #define MCLK_I2S1_8CH_TX 652
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) #define CLK_I2S1_8CH_RX_SRC 653
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) #define CLK_I2S1_8CH_RX_FRAC 654
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) #define CLK_I2S1_8CH_RX 655
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) #define MCLK_I2S1_8CH_RX 656
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) #define I2S1_8CH_MCLKOUT 657
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) #define CLK_PMU1_50M_SRC 658
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) #define CLK_PMU1_100M_SRC 659
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) #define CLK_PMU1_200M_SRC 660
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) #define CLK_PMU1_300M_SRC 661
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) #define CLK_PMU1_400M_SRC 662
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) #define HCLK_PMU1_ROOT 663
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) #define PCLK_PMU1_ROOT 664
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) #define PCLK_PMU0_ROOT 665
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) #define HCLK_PMU_CM0_ROOT 666
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) #define PCLK_PMU1 667
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) #define CLK_DDR_FAIL_SAFE 668
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) #define CLK_PMU1 669
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) #define HCLK_PDM0 670
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) #define MCLK_PDM0 671
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) #define HCLK_VAD 672
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) #define FCLK_PMU_CM0_CORE 673
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) #define CLK_PMU_CM0_RTC 674
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) #define PCLK_PMU1_IOC 675
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) #define PCLK_PMU1PWM 676
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) #define CLK_PMU1PWM 677
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) #define CLK_PMU1PWM_CAPTURE 678
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) #define PCLK_PMU1TIMER 679
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) #define CLK_PMU1TIMER_ROOT 680
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) #define CLK_PMU1TIMER0 681
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) #define CLK_PMU1TIMER1 682
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) #define CLK_UART0_SRC 683
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) #define CLK_UART0_FRAC 684
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) #define CLK_UART0 685
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) #define SCLK_UART0 686
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) #define PCLK_UART0 687
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) #define PCLK_PMU1WDT 688
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) #define TCLK_PMU1WDT 689
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) #define CLK_CR_PARA 690
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) #define CLK_USB2PHY_HDPTXRXPHY_REF 693
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) #define CLK_USBDPPHY_MIPIDCPPHY_REF 694
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) #define CLK_REF_PIPE_PHY0_OSC_SRC 695
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) #define CLK_REF_PIPE_PHY1_OSC_SRC 696
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) #define CLK_REF_PIPE_PHY2_OSC_SRC 697
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) #define CLK_REF_PIPE_PHY0_PLL_SRC 698
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) #define CLK_REF_PIPE_PHY1_PLL_SRC 699
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) #define CLK_REF_PIPE_PHY2_PLL_SRC 700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) #define CLK_REF_PIPE_PHY0 701
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) #define CLK_REF_PIPE_PHY1 702
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) #define CLK_REF_PIPE_PHY2 703
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) #define SCLK_SDIO_DRV 704
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) #define SCLK_SDIO_SAMPLE 705
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) #define SCLK_SDMMC_DRV 706
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) #define SCLK_SDMMC_SAMPLE 707
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) #define CLK_PCIE1L0_PIPE 708
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) #define CLK_PCIE1L1_PIPE 709
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) #define CLK_BIGCORE0_PVTM 710
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) #define CLK_CORE_BIGCORE0_PVTM 711
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) #define CLK_BIGCORE1_PVTM 712
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) #define CLK_CORE_BIGCORE1_PVTM 713
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) #define CLK_LITCORE_PVTM 714
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) #define CLK_CORE_LITCORE_PVTM 715
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) #define CLK_AUX16M_0 716
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) #define CLK_AUX16M_1 717
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) #define CLK_PHY0_REF_ALT_P 718
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) #define CLK_PHY0_REF_ALT_M 719
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) #define CLK_PHY1_REF_ALT_P 720
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) #define CLK_PHY1_REF_ALT_M 721
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) #define CLK_NR_CLKS (CLK_PHY1_REF_ALT_M + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) /********Name=SOFTRST_CON01,Offset=0xA04********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) #define SRST_A_TOP_BIU 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) #define SRST_P_TOP_BIU 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) #define SRST_P_CSIPHY0 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) #define SRST_CSIPHY0 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) #define SRST_P_CSIPHY1 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) #define SRST_CSIPHY1 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) #define SRST_A_TOP_M500_BIU 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) /********Name=SOFTRST_CON02,Offset=0xA08********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) #define SRST_A_TOP_M400_BIU 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) #define SRST_A_TOP_S200_BIU 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) #define SRST_A_TOP_S400_BIU 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) #define SRST_A_TOP_M300_BIU 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) #define SRST_USBDP_COMBO_PHY0_INIT 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) #define SRST_USBDP_COMBO_PHY0_CMN 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) #define SRST_USBDP_COMBO_PHY0_LANE 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) #define SRST_USBDP_COMBO_PHY0_PCS 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) #define SRST_USBDP_COMBO_PHY1_INIT 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) /********Name=SOFTRST_CON03,Offset=0xA0C********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) #define SRST_USBDP_COMBO_PHY1_CMN 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) #define SRST_USBDP_COMBO_PHY1_LANE 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) #define SRST_USBDP_COMBO_PHY1_PCS 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) #define SRST_DCPHY0 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) #define SRST_P_MIPI_DCPHY0 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) #define SRST_P_MIPI_DCPHY0_GRF 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) /********Name=SOFTRST_CON04,Offset=0xA10********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) #define SRST_DCPHY1 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) #define SRST_P_MIPI_DCPHY1 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) #define SRST_P_MIPI_DCPHY1_GRF 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) #define SRST_P_APB2ASB_SLV_CDPHY 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) #define SRST_P_APB2ASB_SLV_CSIPHY 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) #define SRST_P_APB2ASB_SLV_VCCIO3_5 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) #define SRST_P_APB2ASB_SLV_VCCIO6 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) #define SRST_P_APB2ASB_SLV_EMMCIO 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) #define SRST_P_APB2ASB_SLV_IOC_TOP 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) #define SRST_P_APB2ASB_SLV_IOC_RIGHT 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) /********Name=SOFTRST_CON05,Offset=0xA14********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) #define SRST_P_CRU 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) #define SRST_A_CHANNEL_SECURE2VO1USB 87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) #define SRST_A_CHANNEL_SECURE2CENTER 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) #define SRST_H_CHANNEL_SECURE2VO1USB 94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) #define SRST_H_CHANNEL_SECURE2CENTER 95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) /********Name=SOFTRST_CON06,Offset=0xA18********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) #define SRST_P_CHANNEL_SECURE2VO1USB 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) #define SRST_P_CHANNEL_SECURE2CENTER 97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) /********Name=SOFTRST_CON07,Offset=0xA1C********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) #define SRST_H_AUDIO_BIU 114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) #define SRST_P_AUDIO_BIU 115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) #define SRST_H_I2S0_8CH 116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) #define SRST_M_I2S0_8CH_TX 119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) #define SRST_M_I2S0_8CH_RX 122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) #define SRST_P_ACDCDIG 123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) #define SRST_H_I2S2_2CH 124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) #define SRST_H_I2S3_2CH 125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) /********Name=SOFTRST_CON08,Offset=0xA20********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) #define SRST_M_I2S2_2CH 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) #define SRST_M_I2S3_2CH 131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) #define SRST_DAC_ACDCDIG 132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) #define SRST_H_SPDIF0 142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) /********Name=SOFTRST_CON09,Offset=0xA24********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) #define SRST_M_SPDIF0 145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) #define SRST_H_SPDIF1 146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) #define SRST_M_SPDIF1 149
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) #define SRST_H_PDM1 150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) #define SRST_PDM1 151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) /********Name=SOFTRST_CON10,Offset=0xA28********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) #define SRST_A_BUS_BIU 161
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) #define SRST_P_BUS_BIU 162
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) #define SRST_A_GIC 163
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) #define SRST_A_GIC_DBG 164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) #define SRST_A_DMAC0 165
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) #define SRST_A_DMAC1 166
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) #define SRST_A_DMAC2 167
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) #define SRST_P_I2C1 168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) #define SRST_P_I2C2 169
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) #define SRST_P_I2C3 170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) #define SRST_P_I2C4 171
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) #define SRST_P_I2C5 172
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) #define SRST_P_I2C6 173
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) #define SRST_P_I2C7 174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) #define SRST_P_I2C8 175
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) /********Name=SOFTRST_CON11,Offset=0xA2C********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) #define SRST_I2C1 176
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) #define SRST_I2C2 177
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) #define SRST_I2C3 178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) #define SRST_I2C4 179
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) #define SRST_I2C5 180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) #define SRST_I2C6 181
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) #define SRST_I2C7 182
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) #define SRST_I2C8 183
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) #define SRST_P_CAN0 184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) #define SRST_CAN0 185
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) #define SRST_P_CAN1 186
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) #define SRST_CAN1 187
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) #define SRST_P_CAN2 188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) #define SRST_CAN2 189
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) #define SRST_P_SARADC 190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) /********Name=SOFTRST_CON12,Offset=0xA30********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) #define SRST_P_TSADC 192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) #define SRST_TSADC 193
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) #define SRST_P_UART1 194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) #define SRST_P_UART2 195
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) #define SRST_P_UART3 196
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) #define SRST_P_UART4 197
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) #define SRST_P_UART5 198
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) #define SRST_P_UART6 199
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) #define SRST_P_UART7 200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) #define SRST_P_UART8 201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) #define SRST_P_UART9 202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) #define SRST_S_UART1 205
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) /********Name=SOFTRST_CON13,Offset=0xA34********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) #define SRST_S_UART2 208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) #define SRST_S_UART3 211
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) #define SRST_S_UART4 214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) #define SRST_S_UART5 217
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) #define SRST_S_UART6 220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) #define SRST_S_UART7 223
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) /********Name=SOFTRST_CON14,Offset=0xA38********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) #define SRST_S_UART8 226
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) #define SRST_S_UART9 229
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) #define SRST_P_SPI0 230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) #define SRST_P_SPI1 231
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) #define SRST_P_SPI2 232
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) #define SRST_P_SPI3 233
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) #define SRST_P_SPI4 234
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) #define SRST_SPI0 235
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) #define SRST_SPI1 236
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) #define SRST_SPI2 237
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) #define SRST_SPI3 238
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) #define SRST_SPI4 239
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) /********Name=SOFTRST_CON15,Offset=0xA3C********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) #define SRST_P_WDT0 240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) #define SRST_T_WDT0 241
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) #define SRST_P_SYS_GRF 242
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) #define SRST_P_PWM1 243
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) #define SRST_PWM1 244
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) #define SRST_P_PWM2 246
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) #define SRST_PWM2 247
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) #define SRST_P_PWM3 249
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) #define SRST_PWM3 250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) #define SRST_P_BUSTIMER0 252
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) #define SRST_P_BUSTIMER1 253
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) #define SRST_BUSTIMER0 255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) /********Name=SOFTRST_CON16,Offset=0xA40********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) #define SRST_BUSTIMER1 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) #define SRST_BUSTIMER2 257
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) #define SRST_BUSTIMER3 258
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) #define SRST_BUSTIMER4 259
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) #define SRST_BUSTIMER5 260
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) #define SRST_BUSTIMER6 261
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) #define SRST_BUSTIMER7 262
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) #define SRST_BUSTIMER8 263
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) #define SRST_BUSTIMER9 264
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) #define SRST_BUSTIMER10 265
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) #define SRST_BUSTIMER11 266
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) #define SRST_P_MAILBOX0 267
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) #define SRST_P_MAILBOX1 268
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) #define SRST_P_MAILBOX2 269
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) #define SRST_P_GPIO1 270
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) #define SRST_GPIO1 271
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) /********Name=SOFTRST_CON17,Offset=0xA44********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) #define SRST_P_GPIO2 272
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) #define SRST_GPIO2 273
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) #define SRST_P_GPIO3 274
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) #define SRST_GPIO3 275
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) #define SRST_P_GPIO4 276
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) #define SRST_GPIO4 277
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) #define SRST_A_DECOM 278
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) #define SRST_P_DECOM 279
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) #define SRST_D_DECOM 280
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) #define SRST_P_TOP 281
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) #define SRST_A_GICADB_GIC2CORE_BUS 283
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) #define SRST_P_DFT2APB 284
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) #define SRST_P_APB2ASB_MST_TOP 285
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) #define SRST_P_APB2ASB_MST_CDPHY 286
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) #define SRST_P_APB2ASB_MST_BOT_RIGHT 287
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) /********Name=SOFTRST_CON18,Offset=0xA48********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) #define SRST_P_APB2ASB_MST_IOC_TOP 288
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) #define SRST_P_APB2ASB_MST_IOC_RIGHT 289
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) #define SRST_P_APB2ASB_MST_CSIPHY 290
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) #define SRST_P_APB2ASB_MST_VCCIO3_5 291
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) #define SRST_P_APB2ASB_MST_VCCIO6 292
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) #define SRST_P_APB2ASB_MST_EMMCIO 293
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) #define SRST_A_SPINLOCK 294
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) #define SRST_P_OTPC_NS 297
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) #define SRST_OTPC_NS 298
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) #define SRST_OTPC_ARB 299
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) /********Name=SOFTRST_CON19,Offset=0xA4C********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) #define SRST_P_BUSIOC 304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) #define SRST_P_PMUCM0_INTMUX 308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) #define SRST_P_DDRCM0_INTMUX 309
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) /********Name=SOFTRST_CON20,Offset=0xA50********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) #define SRST_P_DDR_DFICTL_CH0 320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) #define SRST_P_DDR_MON_CH0 321
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) #define SRST_P_DDR_STANDBY_CH0 322
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) #define SRST_P_DDR_UPCTL_CH0 323
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) #define SRST_TM_DDR_MON_CH0 324
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) #define SRST_P_DDR_GRF_CH01 325
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) #define SRST_DFI_CH0 326
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) #define SRST_SBR_CH0 327
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) #define SRST_DDR_UPCTL_CH0 328
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) #define SRST_DDR_DFICTL_CH0 329
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) #define SRST_DDR_MON_CH0 330
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) #define SRST_DDR_STANDBY_CH0 331
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) #define SRST_A_DDR_UPCTL_CH0 332
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) #define SRST_P_DDR_DFICTL_CH1 333
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) #define SRST_P_DDR_MON_CH1 334
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) #define SRST_P_DDR_STANDBY_CH1 335
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) /********Name=SOFTRST_CON21,Offset=0xA54********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) #define SRST_P_DDR_UPCTL_CH1 336
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) #define SRST_TM_DDR_MON_CH1 337
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) #define SRST_DFI_CH1 338
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) #define SRST_SBR_CH1 339
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) #define SRST_DDR_UPCTL_CH1 340
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) #define SRST_DDR_DFICTL_CH1 341
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) #define SRST_DDR_MON_CH1 342
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) #define SRST_DDR_STANDBY_CH1 343
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) #define SRST_A_DDR_UPCTL_CH1 344
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) #define SRST_A_DDR01_MSCH0 349
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) #define SRST_A_DDR01_RS_MSCH0 350
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) #define SRST_A_DDR01_FRS_MSCH0 351
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) /********Name=SOFTRST_CON22,Offset=0xA58********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) #define SRST_A_DDR01_SCRAMBLE0 352
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) #define SRST_A_DDR01_FRS_SCRAMBLE0 353
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) #define SRST_A_DDR01_MSCH1 354
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) #define SRST_A_DDR01_RS_MSCH1 355
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) #define SRST_A_DDR01_FRS_MSCH1 356
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) #define SRST_A_DDR01_SCRAMBLE1 357
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) #define SRST_A_DDR01_FRS_SCRAMBLE1 358
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) #define SRST_P_DDR01_MSCH0 359
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) #define SRST_P_DDR01_MSCH1 360
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) /********Name=SOFTRST_CON23,Offset=0xA5C********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) #define SRST_P_DDR_DFICTL_CH2 368
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) #define SRST_P_DDR_MON_CH2 369
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) #define SRST_P_DDR_STANDBY_CH2 370
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) #define SRST_P_DDR_UPCTL_CH2 371
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) #define SRST_TM_DDR_MON_CH2 372
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) #define SRST_P_DDR_GRF_CH23 373
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) #define SRST_DFI_CH2 374
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) #define SRST_SBR_CH2 375
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) #define SRST_DDR_UPCTL_CH2 376
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) #define SRST_DDR_DFICTL_CH2 377
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) #define SRST_DDR_MON_CH2 378
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) #define SRST_DDR_STANDBY_CH2 379
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) #define SRST_A_DDR_UPCTL_CH2 380
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) #define SRST_P_DDR_DFICTL_CH3 381
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) #define SRST_P_DDR_MON_CH3 382
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) #define SRST_P_DDR_STANDBY_CH3 383
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) /********Name=SOFTRST_CON24,Offset=0xA60********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) #define SRST_P_DDR_UPCTL_CH3 384
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) #define SRST_TM_DDR_MON_CH3 385
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) #define SRST_DFI_CH3 386
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) #define SRST_SBR_CH3 387
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) #define SRST_DDR_UPCTL_CH3 388
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) #define SRST_DDR_DFICTL_CH3 389
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) #define SRST_DDR_MON_CH3 390
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) #define SRST_DDR_STANDBY_CH3 391
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) #define SRST_A_DDR_UPCTL_CH3 392
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) #define SRST_A_DDR23_MSCH2 397
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) #define SRST_A_DDR23_RS_MSCH2 398
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) #define SRST_A_DDR23_FRS_MSCH2 399
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) /********Name=SOFTRST_CON25,Offset=0xA64********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) #define SRST_A_DDR23_SCRAMBLE2 400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) #define SRST_A_DDR23_FRS_SCRAMBLE2 401
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) #define SRST_A_DDR23_MSCH3 402
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) #define SRST_A_DDR23_RS_MSCH3 403
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) #define SRST_A_DDR23_FRS_MSCH3 404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) #define SRST_A_DDR23_SCRAMBLE3 405
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) #define SRST_A_DDR23_FRS_SCRAMBLE3 406
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) #define SRST_P_DDR23_MSCH2 407
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) #define SRST_P_DDR23_MSCH3 408
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) /********Name=SOFTRST_CON26,Offset=0xA68********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) #define SRST_ISP1 419
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) #define SRST_ISP1_VICAP 420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) #define SRST_A_ISP1_BIU 422
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) #define SRST_H_ISP1_BIU 424
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) /********Name=SOFTRST_CON27,Offset=0xA6C********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) #define SRST_A_RKNN1 432
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) #define SRST_A_RKNN1_BIU 433
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) #define SRST_H_RKNN1 434
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) #define SRST_H_RKNN1_BIU 435
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) /********Name=SOFTRST_CON28,Offset=0xA70********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) #define SRST_A_RKNN2 448
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) #define SRST_A_RKNN2_BIU 449
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) #define SRST_H_RKNN2 450
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) #define SRST_H_RKNN2_BIU 451
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) /********Name=SOFTRST_CON29,Offset=0xA74********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) #define SRST_A_RKNN_DSU0 467
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) #define SRST_P_NPUTOP_BIU 469
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) #define SRST_P_NPU_TIMER 470
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) #define SRST_NPUTIMER0 472
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) #define SRST_NPUTIMER1 473
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) #define SRST_P_NPU_WDT 474
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) #define SRST_T_NPU_WDT 475
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) #define SRST_P_NPU_PVTM 476
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) #define SRST_P_NPU_GRF 477
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) #define SRST_NPU_PVTM 478
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) /********Name=SOFTRST_CON30,Offset=0xA78********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) #define SRST_NPU_PVTPLL 480
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) #define SRST_H_NPU_CM0_BIU 482
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) #define SRST_F_NPU_CM0_CORE 483
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) #define SRST_T_NPU_CM0_JTAG 484
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) #define SRST_A_RKNN0 486
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) #define SRST_A_RKNN0_BIU 487
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) #define SRST_H_RKNN0 488
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) #define SRST_H_RKNN0_BIU 489
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) /********Name=SOFTRST_CON31,Offset=0xA7C********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) #define SRST_H_NVM_BIU 498
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) #define SRST_A_NVM_BIU 499
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) #define SRST_H_EMMC 500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) #define SRST_A_EMMC 501
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) #define SRST_C_EMMC 502
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) #define SRST_B_EMMC 503
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) #define SRST_T_EMMC 504
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) #define SRST_S_SFC 505
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) #define SRST_H_SFC 506
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) #define SRST_H_SFC_XIP 507
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) /********Name=SOFTRST_CON32,Offset=0xA80********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) #define SRST_P_GRF 513
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) #define SRST_P_DEC_BIU 514
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) #define SRST_P_PHP_BIU 517
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) #define SRST_A_PCIE_GRIDGE 520
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) #define SRST_A_PHP_BIU 521
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) #define SRST_A_GMAC0 522
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) #define SRST_A_GMAC1 523
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) #define SRST_A_PCIE_BIU 524
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) #define SRST_PCIE0_POWER_UP 525
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) #define SRST_PCIE1_POWER_UP 526
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) #define SRST_PCIE2_POWER_UP 527
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) /********Name=SOFTRST_CON33,Offset=0xA84********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) #define SRST_PCIE3_POWER_UP 528
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) #define SRST_PCIE4_POWER_UP 529
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) #define SRST_P_PCIE0 540
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) #define SRST_P_PCIE1 541
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) #define SRST_P_PCIE2 542
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) #define SRST_P_PCIE3 543
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) /********Name=SOFTRST_CON34,Offset=0xA88********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) #define SRST_P_PCIE4 544
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) #define SRST_A_PHP_GIC_ITS 550
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) #define SRST_A_MMU_PCIE 551
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) #define SRST_A_MMU_PHP 552
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) #define SRST_A_MMU_BIU 553
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) /********Name=SOFTRST_CON35,Offset=0xA8C********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) #define SRST_A_USB3OTG2 567
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) /********Name=SOFTRST_CON37,Offset=0xA94********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) #define SRST_PMALIVE0 596
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) #define SRST_PMALIVE1 597
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) #define SRST_PMALIVE2 598
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) #define SRST_A_SATA0 599
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) #define SRST_A_SATA1 600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) #define SRST_A_SATA2 601
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) #define SRST_RXOOB0 602
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) #define SRST_RXOOB1 603
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) #define SRST_RXOOB2 604
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) #define SRST_ASIC0 605
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) #define SRST_ASIC1 606
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) #define SRST_ASIC2 607
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) /********Name=SOFTRST_CON40,Offset=0xAA0********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) #define SRST_A_RKVDEC_CCU 642
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) #define SRST_H_RKVDEC0 643
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) #define SRST_A_RKVDEC0 644
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) #define SRST_H_RKVDEC0_BIU 645
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) #define SRST_A_RKVDEC0_BIU 646
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) #define SRST_RKVDEC0_CA 647
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) #define SRST_RKVDEC0_HEVC_CA 648
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) #define SRST_RKVDEC0_CORE 649
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) /********Name=SOFTRST_CON41,Offset=0xAA4********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) #define SRST_H_RKVDEC1 658
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) #define SRST_A_RKVDEC1 659
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) #define SRST_H_RKVDEC1_BIU 660
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) #define SRST_A_RKVDEC1_BIU 661
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) #define SRST_RKVDEC1_CA 662
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) #define SRST_RKVDEC1_HEVC_CA 663
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) #define SRST_RKVDEC1_CORE 664
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) /********Name=SOFTRST_CON42,Offset=0xAA8********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) #define SRST_A_USB_BIU 674
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) #define SRST_H_USB_BIU 675
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) #define SRST_A_USB3OTG0 676
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) #define SRST_A_USB3OTG1 679
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) #define SRST_H_HOST0 682
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) #define SRST_H_HOST_ARB0 683
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) #define SRST_H_HOST1 684
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) #define SRST_H_HOST_ARB1 685
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) #define SRST_A_USB_GRF 686
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) #define SRST_C_USB2P0_HOST0 687
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) /********Name=SOFTRST_CON43,Offset=0xAAC********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) #define SRST_C_USB2P0_HOST1 688
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) #define SRST_HOST_UTMI0 689
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) #define SRST_HOST_UTMI1 690
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) /********Name=SOFTRST_CON44,Offset=0xAB0********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) #define SRST_A_VDPU_BIU 708
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) #define SRST_A_VDPU_LOW_BIU 709
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) #define SRST_H_VDPU_BIU 710
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) #define SRST_A_JPEG_DECODER_BIU 711
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) #define SRST_A_VPU 712
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) #define SRST_H_VPU 713
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) #define SRST_A_JPEG_ENCODER0 714
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) #define SRST_H_JPEG_ENCODER0 715
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) #define SRST_A_JPEG_ENCODER1 716
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) #define SRST_H_JPEG_ENCODER1 717
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) #define SRST_A_JPEG_ENCODER2 718
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) #define SRST_H_JPEG_ENCODER2 719
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) /********Name=SOFTRST_CON45,Offset=0xAB4********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) #define SRST_A_JPEG_ENCODER3 720
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) #define SRST_H_JPEG_ENCODER3 721
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) #define SRST_A_JPEG_DECODER 722
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) #define SRST_H_JPEG_DECODER 723
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) #define SRST_H_IEP2P0 724
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) #define SRST_A_IEP2P0 725
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) #define SRST_IEP2P0_CORE 726
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) #define SRST_H_RGA2 727
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) #define SRST_A_RGA2 728
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) #define SRST_RGA2_CORE 729
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) #define SRST_H_RGA3_0 730
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) #define SRST_A_RGA3_0 731
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) #define SRST_RGA3_0_CORE 732
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) /********Name=SOFTRST_CON47,Offset=0xABC********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) #define SRST_H_RKVENC0_BIU 754
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) #define SRST_A_RKVENC0_BIU 755
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) #define SRST_H_RKVENC0 756
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) #define SRST_A_RKVENC0 757
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) #define SRST_RKVENC0_CORE 758
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) /********Name=SOFTRST_CON48,Offset=0xAC0********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) #define SRST_H_RKVENC1_BIU 770
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) #define SRST_A_RKVENC1_BIU 771
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) #define SRST_H_RKVENC1 772
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) #define SRST_A_RKVENC1 773
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) #define SRST_RKVENC1_CORE 774
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) /********Name=SOFTRST_CON49,Offset=0xAC4********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) #define SRST_A_VI_BIU 787
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) #define SRST_H_VI_BIU 788
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) #define SRST_P_VI_BIU 789
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) #define SRST_D_VICAP 790
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) #define SRST_A_VICAP 791
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) #define SRST_H_VICAP 792
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) #define SRST_ISP0 794
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) #define SRST_ISP0_VICAP 795
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) /********Name=SOFTRST_CON50,Offset=0xAC8********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) #define SRST_FISHEYE0 800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) #define SRST_FISHEYE1 803
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) #define SRST_P_CSI_HOST_0 804
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) #define SRST_P_CSI_HOST_1 805
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) #define SRST_P_CSI_HOST_2 806
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) #define SRST_P_CSI_HOST_3 807
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) #define SRST_P_CSI_HOST_4 808
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) #define SRST_P_CSI_HOST_5 809
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) /********Name=SOFTRST_CON51,Offset=0xACC********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) #define SRST_CSIHOST0_VICAP 820
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) #define SRST_CSIHOST1_VICAP 821
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) #define SRST_CSIHOST2_VICAP 822
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) #define SRST_CSIHOST3_VICAP 823
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) #define SRST_CSIHOST4_VICAP 824
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) #define SRST_CSIHOST5_VICAP 825
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) #define SRST_CIFIN 829
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) /********Name=SOFTRST_CON52,Offset=0xAD0********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) #define SRST_A_VOP_BIU 836
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) #define SRST_A_VOP_LOW_BIU 837
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) #define SRST_H_VOP_BIU 838
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) #define SRST_P_VOP_BIU 839
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) #define SRST_H_VOP 840
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) #define SRST_A_VOP 841
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) #define SRST_D_VOP0 845
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) #define SRST_D_VOP2HDMI_BRIDGE0 846
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) #define SRST_D_VOP2HDMI_BRIDGE1 847
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) /********Name=SOFTRST_CON53,Offset=0xAD4********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) #define SRST_D_VOP1 848
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) #define SRST_D_VOP2 849
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) #define SRST_D_VOP3 850
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) #define SRST_P_VOPGRF 851
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) #define SRST_P_DSIHOST0 852
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) #define SRST_P_DSIHOST1 853
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) #define SRST_DSIHOST0 854
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) #define SRST_DSIHOST1 855
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) #define SRST_VOP_PMU 856
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) #define SRST_P_VOP_CHANNEL_BIU 857
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) /********Name=SOFTRST_CON55,Offset=0xADC********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) #define SRST_H_VO0_BIU 885
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) #define SRST_H_VO0_S_BIU 886
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) #define SRST_P_VO0_BIU 887
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) #define SRST_P_VO0_S_BIU 888
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) #define SRST_A_HDCP0_BIU 889
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) #define SRST_P_VO0GRF 890
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) #define SRST_H_HDCP_KEY0 891
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) #define SRST_A_HDCP0 892
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) #define SRST_H_HDCP0 893
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) #define SRST_HDCP0 895
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) /********Name=SOFTRST_CON56,Offset=0xAE0********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) #define SRST_P_TRNG0 897
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) #define SRST_DP0 904
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) #define SRST_DP1 905
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) #define SRST_H_I2S4_8CH 906
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) #define SRST_M_I2S4_8CH_TX 909
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) #define SRST_H_I2S8_8CH 910
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) /********Name=SOFTRST_CON57,Offset=0xAE4********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) #define SRST_M_I2S8_8CH_TX 913
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) #define SRST_H_SPDIF2_DP0 914
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) #define SRST_M_SPDIF2_DP0 918
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) #define SRST_H_SPDIF5_DP1 919
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) #define SRST_M_SPDIF5_DP1 923
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) /********Name=SOFTRST_CON59,Offset=0xAEC********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) #define SRST_A_HDCP1_BIU 950
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) #define SRST_A_HDMIRX_BIU 951
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) #define SRST_A_VO1_BIU 952
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) #define SRST_H_VOP1_BIU 953
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) #define SRST_H_VOP1_S_BIU 954
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) #define SRST_P_VOP1_BIU 955
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) #define SRST_P_VO1GRF 956
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) #define SRST_P_VO1_S_BIU 957
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) /********Name=SOFTRST_CON60,Offset=0xAF0********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) #define SRST_H_I2S7_8CH 960
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) #define SRST_M_I2S7_8CH_RX 963
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) #define SRST_H_HDCP_KEY1 964
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) #define SRST_A_HDCP1 965
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) #define SRST_H_HDCP1 966
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) #define SRST_HDCP1 968
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) #define SRST_P_TRNG1 970
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) #define SRST_P_HDMITX0 971
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) /********Name=SOFTRST_CON61,Offset=0xAF4********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) #define SRST_HDMITX0_REF 976
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) #define SRST_P_HDMITX1 978
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) #define SRST_HDMITX1_REF 983
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) #define SRST_A_HDMIRX 985
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) #define SRST_P_HDMIRX 986
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) #define SRST_HDMIRX_REF 987
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) /********Name=SOFTRST_CON62,Offset=0xAF8********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) #define SRST_P_EDP0 992
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) #define SRST_EDP0_24M 993
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) #define SRST_P_EDP1 995
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) #define SRST_EDP1_24M 996
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) #define SRST_M_I2S5_8CH_TX 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) #define SRST_H_I2S5_8CH 1004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) #define SRST_M_I2S6_8CH_TX 1007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) /********Name=SOFTRST_CON63,Offset=0xAFC********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) #define SRST_M_I2S6_8CH_RX 1010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) #define SRST_H_I2S6_8CH 1011
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) #define SRST_H_SPDIF3 1012
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) #define SRST_M_SPDIF3 1015
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) #define SRST_H_SPDIF4 1016
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) #define SRST_M_SPDIF4 1019
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) #define SRST_H_SPDIFRX0 1020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) #define SRST_M_SPDIFRX0 1021
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) #define SRST_H_SPDIFRX1 1022
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) #define SRST_M_SPDIFRX1 1023
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) /********Name=SOFTRST_CON64,Offset=0xB00********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) #define SRST_H_SPDIFRX2 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) #define SRST_M_SPDIFRX2 1025
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) #define SRST_LINKSYM_HDMITXPHY0 1036
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) #define SRST_LINKSYM_HDMITXPHY1 1037
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) #define SRST_VO1_BRIDGE0 1038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) #define SRST_VO1_BRIDGE1 1039
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) /********Name=SOFTRST_CON65,Offset=0xB04********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) #define SRST_H_I2S9_8CH 1040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) #define SRST_M_I2S9_8CH_RX 1043
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) #define SRST_H_I2S10_8CH 1044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) #define SRST_M_I2S10_8CH_RX 1047
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) #define SRST_P_S_HDMIRX 1048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) /********Name=SOFTRST_CON66,Offset=0xB08********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) #define SRST_GPU 1060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) #define SRST_SYS_GPU 1061
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) #define SRST_A_S_GPU_BIU 1064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) #define SRST_A_M0_GPU_BIU 1065
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) #define SRST_A_M1_GPU_BIU 1066
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) #define SRST_A_M2_GPU_BIU 1067
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) #define SRST_A_M3_GPU_BIU 1068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) #define SRST_P_GPU_BIU 1070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) #define SRST_P_GPU_PVTM 1071
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) /********Name=SOFTRST_CON67,Offset=0xB0C********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) #define SRST_GPU_PVTM 1072
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) #define SRST_P_GPU_GRF 1074
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) #define SRST_GPU_PVTPLL 1075
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) #define SRST_GPU_JTAG 1076
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) /********Name=SOFTRST_CON68,Offset=0xB10********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) #define SRST_A_AV1_BIU 1089
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) #define SRST_A_AV1 1090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) #define SRST_P_AV1_BIU 1092
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) #define SRST_P_AV1 1093
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) /********Name=SOFTRST_CON69,Offset=0xB14********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) #define SRST_A_DDR_BIU 1108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) #define SRST_A_DMA2DDR 1109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) #define SRST_A_DDR_SHAREMEM 1110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) #define SRST_A_DDR_SHAREMEM_BIU 1111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) #define SRST_A_CENTER_S200_BIU 1114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) #define SRST_A_CENTER_S400_BIU 1115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) #define SRST_H_AHB2APB 1116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) #define SRST_H_CENTER_BIU 1117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) #define SRST_F_DDR_CM0_CORE 1118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) /********Name=SOFTRST_CON70,Offset=0xB18********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) #define SRST_DDR_TIMER0 1120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) #define SRST_DDR_TIMER1 1121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) #define SRST_T_WDT_DDR 1122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) #define SRST_T_DDR_CM0_JTAG 1123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) #define SRST_P_CENTER_GRF 1125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) #define SRST_P_AHB2APB 1126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) #define SRST_P_WDT 1127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) #define SRST_P_TIMER 1128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) #define SRST_P_DMA2DDR 1129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) #define SRST_P_SHAREMEM 1130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) #define SRST_P_CENTER_BIU 1131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) #define SRST_P_CENTER_CHANNEL_BIU 1132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) /********Name=SOFTRST_CON72,Offset=0xB20********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) #define SRST_P_USBDPGRF0 1153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) #define SRST_P_USBDPPHY0 1154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) #define SRST_P_USBDPGRF1 1155
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) #define SRST_P_USBDPPHY1 1156
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) #define SRST_P_HDPTX0 1157
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) #define SRST_P_HDPTX1 1158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) #define SRST_P_APB2ASB_SLV_BOT_RIGHT 1159
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) #define SRST_P_USB2PHY_U3_0_GRF0 1160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) #define SRST_P_USB2PHY_U3_1_GRF0 1161
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) #define SRST_P_USB2PHY_U2_0_GRF0 1162
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) #define SRST_P_USB2PHY_U2_1_GRF0 1163
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) #define SRST_HDPTX0_ROPLL 1164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) #define SRST_HDPTX0_LCPLL 1165
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) #define SRST_HDPTX0 1166
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) #define SRST_HDPTX1_ROPLL 1167
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) /********Name=SOFTRST_CON73,Offset=0xB24********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) #define SRST_HDPTX1_LCPLL 1168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) #define SRST_HDPTX1 1169
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) #define SRST_HDPTX0_HDMIRXPHY_SET 1170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) #define SRST_USBDP_COMBO_PHY0 1171
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) #define SRST_USBDP_COMBO_PHY0_LCPLL 1172
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) #define SRST_USBDP_COMBO_PHY0_ROPLL 1173
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) #define SRST_USBDP_COMBO_PHY0_PCS_HS 1174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) #define SRST_USBDP_COMBO_PHY1 1175
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) #define SRST_USBDP_COMBO_PHY1_LCPLL 1176
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) #define SRST_USBDP_COMBO_PHY1_ROPLL 1177
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) #define SRST_USBDP_COMBO_PHY1_PCS_HS 1178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) #define SRST_HDMIHDP0 1180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) #define SRST_HDMIHDP1 1181
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) /********Name=SOFTRST_CON74,Offset=0xB28********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) #define SRST_A_VO1USB_TOP_BIU 1185
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) #define SRST_H_VO1USB_TOP_BIU 1187
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) /********Name=SOFTRST_CON75,Offset=0xB2C********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) #define SRST_H_SDIO_BIU 1201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) #define SRST_H_SDIO 1202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) #define SRST_SDIO 1203
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) /********Name=SOFTRST_CON76,Offset=0xB30********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) #define SRST_H_RGA3_BIU 1218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) #define SRST_A_RGA3_BIU 1219
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) #define SRST_H_RGA3_1 1220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) #define SRST_A_RGA3_1 1221
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) #define SRST_RGA3_1_CORE 1222
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) /********Name=SOFTRST_CON77,Offset=0xB34********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) #define SRST_REF_PIPE_PHY0 1238
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) #define SRST_REF_PIPE_PHY1 1239
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) #define SRST_REF_PIPE_PHY2 1240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) /********Name=PHPTOPSOFTRST_CON0,Offset=0x8A00********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) #define SRST_P_PHPTOP_CRU 131073
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) #define SRST_P_PCIE2_GRF0 131074
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) #define SRST_P_PCIE2_GRF1 131075
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) #define SRST_P_PCIE2_GRF2 131076
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) #define SRST_P_PCIE2_PHY0 131077
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) #define SRST_P_PCIE2_PHY1 131078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) #define SRST_P_PCIE2_PHY2 131079
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) #define SRST_P_PCIE3_PHY 131080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) #define SRST_P_APB2ASB_SLV_CHIP_TOP 131081
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) #define SRST_PCIE30_PHY 131082
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) /********Name=PMU1SOFTRST_CON00,Offset=0x30A00********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) #define SRST_H_PMU1_BIU 786442
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) #define SRST_P_PMU1_BIU 786443
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) #define SRST_H_PMU_CM0_BIU 786444
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) #define SRST_F_PMU_CM0_CORE 786445
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) #define SRST_T_PMU1_CM0_JTAG 786446
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) /********Name=PMU1SOFTRST_CON01,Offset=0x30A04********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) #define SRST_DDR_FAIL_SAFE 786449
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) #define SRST_P_CRU_PMU1 786450
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) #define SRST_P_PMU1_GRF 786452
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) #define SRST_P_PMU1_IOC 786453
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) #define SRST_P_PMU1WDT 786454
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) #define SRST_T_PMU1WDT 786455
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) #define SRST_P_PMU1TIMER 786456
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) #define SRST_PMU1TIMER0 786458
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) #define SRST_PMU1TIMER1 786459
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) #define SRST_P_PMU1PWM 786460
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) #define SRST_PMU1PWM 786461
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) /********Name=PMU1SOFTRST_CON02,Offset=0x30A08********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) #define SRST_P_I2C0 786465
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) #define SRST_I2C0 786466
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) #define SRST_S_UART0 786469
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) #define SRST_P_UART0 786470
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) #define SRST_H_I2S1_8CH 786471
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) #define SRST_M_I2S1_8CH_TX 786474
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) #define SRST_M_I2S1_8CH_RX 786477
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) #define SRST_H_PDM0 786478
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) #define SRST_PDM0 786479
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) /********Name=PMU1SOFTRST_CON03,Offset=0x30A0C********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) #define SRST_H_VAD 786480
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) #define SRST_HDPTX0_INIT 786491
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) #define SRST_HDPTX0_CMN 786492
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) #define SRST_HDPTX0_LANE 786493
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) #define SRST_HDPTX1_INIT 786495
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) /********Name=PMU1SOFTRST_CON04,Offset=0x30A10********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) #define SRST_HDPTX1_CMN 786496
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) #define SRST_HDPTX1_LANE 786497
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) #define SRST_M_MIPI_DCPHY0 786499
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) #define SRST_S_MIPI_DCPHY0 786500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) #define SRST_M_MIPI_DCPHY1 786501
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) #define SRST_S_MIPI_DCPHY1 786502
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) #define SRST_OTGPHY_U3_0 786503
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) #define SRST_OTGPHY_U3_1 786504
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) #define SRST_OTGPHY_U2_0 786505
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) #define SRST_OTGPHY_U2_1 786506
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) /********Name=PMU1SOFTRST_CON05,Offset=0x30A14********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) #define SRST_P_PMU0GRF 786515
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) #define SRST_P_PMU0IOC 786516
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) #define SRST_P_GPIO0 786517
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) #define SRST_GPIO0 786518
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) /* scmi-clocks indices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) #define SCMI_CLK_CPUL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) #define SCMI_CLK_DSU 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) #define SCMI_CLK_CPUB01 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) #define SCMI_CLK_CPUB23 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) #define SCMI_CLK_DDR 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) #define SCMI_CLK_GPU 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) #define SCMI_CLK_NPU 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) #define SCMI_CLK_SBUS 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) #define SCMI_PCLK_SBUS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) #define SCMI_CCLK_SD 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) #define SCMI_DCLK_SD 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) #define SCMI_ACLK_SECURE_NS 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) #define SCMI_HCLK_SECURE_NS 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) #define SCMI_TCLK_WDT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) #define SCMI_KEYLADDER_CORE 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) #define SCMI_KEYLADDER_RNG 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) #define SCMI_ACLK_SECURE_S 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) #define SCMI_HCLK_SECURE_S 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) #define SCMI_PCLK_SECURE_S 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) #define SCMI_CRYPTO_RNG 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) #define SCMI_CRYPTO_CORE 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) #define SCMI_CRYPTO_PKA 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) #define SCMI_SPLL 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) #define SCMI_HCLK_SD 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) /********Name=SECURE_SOFTRST_CON00,Offset=0xA00********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) #define SRST_A_SECURE_NS_BIU 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) #define SRST_H_SECURE_NS_BIU 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) #define SRST_A_SECURE_S_BIU 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) #define SRST_H_SECURE_S_BIU 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) #define SRST_P_SECURE_S_BIU 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) #define SRST_CRYPTO_CORE 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) /********Name=SECURE_SOFTRST_CON01,Offset=0xA04********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) #define SRST_CRYPTO_PKA 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) #define SRST_CRYPTO_RNG 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) #define SRST_A_CRYPTO 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) #define SRST_H_CRYPTO 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) #define SRST_KEYLADDER_CORE 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) #define SRST_KEYLADDER_RNG 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) #define SRST_A_KEYLADDER 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) #define SRST_H_KEYLADDER 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) #define SRST_P_OTPC_S 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) #define SRST_OTPC_S 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) #define SRST_WDT_S 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) /********Name=SECURE_SOFTRST_CON02,Offset=0xA08********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) #define SRST_T_WDT_S 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) #define SRST_H_BOOTROM 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) #define SRST_A_DCF 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) #define SRST_P_DCF 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) #define SRST_H_BOOTROM_NS 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) #define SRST_P_KEYLADDER 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) #define SRST_H_TRNG_S 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) /********Name=SECURE_SOFTRST_CON03,Offset=0xA0C********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) #define SRST_H_TRNG_NS 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) #define SRST_D_SDMMC_BUFFER 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) #define SRST_H_SDMMC 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) #define SRST_H_SDMMC_BUFFER 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) #define SRST_SDMMC 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) #define SRST_P_TRNG_CHK 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) #define SRST_TRNG_S 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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