^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2020 Rockchip Electronics Co. Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Elaine Zhang <zhangqing@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3568_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define _DT_BINDINGS_CLK_ROCKCHIP_RK3568_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /* pmucru-clocks indices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /* pmucru plls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define PLL_PPLL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define PLL_HPLL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* pmucru clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define XIN_OSC0_DIV 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CLK_RTC_32K 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CLK_PMU 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CLK_I2C0 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CLK_RTC32K_FRAC 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CLK_UART0_DIV 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CLK_UART0_FRAC 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SCLK_UART0 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define DBCLK_GPIO0 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CLK_PWM0 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CLK_CAPTURE_PWM0_NDFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CLK_PMUPVTM 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CLK_CORE_PMUPVTM 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CLK_REF24M 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define XIN_OSC0_USBPHY0_G 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CLK_USBPHY0_REF 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define XIN_OSC0_USBPHY1_G 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CLK_USBPHY1_REF 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define XIN_OSC0_MIPIDSIPHY0_G 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CLK_MIPIDSIPHY0_REF 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define XIN_OSC0_MIPIDSIPHY1_G 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CLK_MIPIDSIPHY1_REF 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CLK_WIFI_DIV 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CLK_WIFI_OSC0 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CLK_WIFI 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CLK_PCIEPHY0_DIV 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CLK_PCIEPHY0_OSC0 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CLK_PCIEPHY0_REF 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CLK_PCIEPHY1_DIV 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CLK_PCIEPHY1_OSC0 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CLK_PCIEPHY1_REF 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CLK_PCIEPHY2_DIV 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CLK_PCIEPHY2_OSC0 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CLK_PCIEPHY2_REF 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CLK_PCIE30PHY_REF_M 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CLK_PCIE30PHY_REF_N 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CLK_HDMI_REF 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define XIN_OSC0_EDPPHY_G 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PCLK_PDPMU 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PCLK_PMU 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PCLK_UART0 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PCLK_I2C0 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PCLK_GPIO0 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define PCLK_PMUPVTM 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define PCLK_PWM0 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CLK_PDPMU 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SCLK_32K_IOE 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define CLKPMU_NR_CLKS (SCLK_32K_IOE + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* cru-clocks indices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* cru plls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define PLL_APLL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define PLL_DPLL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define PLL_CPLL 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define PLL_GPLL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define PLL_VPLL 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define PLL_NPLL 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* cru clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define CPLL_333M 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define ARMCLK 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define USB480M 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define ACLK_CORE_NIU2BUS 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define CLK_CORE_PVTM 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define CLK_CORE_PVTM_CORE 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define CLK_CORE_PVTPLL 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define CLK_GPU_SRC 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define CLK_GPU_PRE_NDFT 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define CLK_GPU_PRE_MUX 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define ACLK_GPU_PRE 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define PCLK_GPU_PRE 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define CLK_GPU 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define CLK_GPU_NP5 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define PCLK_GPU_PVTM 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define CLK_GPU_PVTM 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define CLK_GPU_PVTM_CORE 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define CLK_GPU_PVTPLL 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define CLK_NPU_SRC 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define CLK_NPU_PRE_NDFT 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define CLK_NPU 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define CLK_NPU_NP5 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define HCLK_NPU_PRE 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define PCLK_NPU_PRE 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define ACLK_NPU_PRE 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define ACLK_NPU 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define HCLK_NPU 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define PCLK_NPU_PVTM 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define CLK_NPU_PVTM 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define CLK_NPU_PVTM_CORE 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define CLK_NPU_PVTPLL 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define CLK_DDRPHY1X_SRC 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define CLK_DDRPHY1X_HWFFC_SRC 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define CLK_DDR1X 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define CLK_MSCH 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define CLK24_DDRMON 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define ACLK_GIC_AUDIO 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define HCLK_GIC_AUDIO 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define HCLK_SDMMC_BUFFER 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define DCLK_SDMMC_BUFFER 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define ACLK_GIC600 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define ACLK_SPINLOCK 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define HCLK_I2S0_8CH 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define HCLK_I2S1_8CH 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define HCLK_I2S2_2CH 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define HCLK_I2S3_2CH 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define CLK_I2S0_8CH_TX_SRC 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define CLK_I2S0_8CH_TX_FRAC 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define MCLK_I2S0_8CH_TX 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define I2S0_MCLKOUT_TX 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define CLK_I2S0_8CH_RX_SRC 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define CLK_I2S0_8CH_RX_FRAC 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define MCLK_I2S0_8CH_RX 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define I2S0_MCLKOUT_RX 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define CLK_I2S1_8CH_TX_SRC 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define CLK_I2S1_8CH_TX_FRAC 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define MCLK_I2S1_8CH_TX 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define I2S1_MCLKOUT_TX 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define CLK_I2S1_8CH_RX_SRC 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define CLK_I2S1_8CH_RX_FRAC 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define MCLK_I2S1_8CH_RX 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define I2S1_MCLKOUT_RX 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define CLK_I2S2_2CH_SRC 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define CLK_I2S2_2CH_FRAC 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define MCLK_I2S2_2CH 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define I2S2_MCLKOUT 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define CLK_I2S3_2CH_TX_SRC 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define CLK_I2S3_2CH_TX_FRAC 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define MCLK_I2S3_2CH_TX 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define I2S3_MCLKOUT_TX 84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define CLK_I2S3_2CH_RX_SRC 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define CLK_I2S3_2CH_RX_FRAC 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define MCLK_I2S3_2CH_RX 87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define I2S3_MCLKOUT_RX 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define HCLK_PDM 89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define MCLK_PDM 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define HCLK_VAD 91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define HCLK_SPDIF_8CH 92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define MCLK_SPDIF_8CH_SRC 93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define MCLK_SPDIF_8CH_FRAC 94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define MCLK_SPDIF_8CH 95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define HCLK_AUDPWM 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define SCLK_AUDPWM_SRC 97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define SCLK_AUDPWM_FRAC 98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define SCLK_AUDPWM 99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define HCLK_ACDCDIG 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define CLK_ACDCDIG_I2C 101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define CLK_ACDCDIG_DAC 102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define CLK_ACDCDIG_ADC 103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define ACLK_SECURE_FLASH 104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define HCLK_SECURE_FLASH 105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define ACLK_CRYPTO_NS 106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define HCLK_CRYPTO_NS 107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define CLK_CRYPTO_NS_CORE 108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define CLK_CRYPTO_NS_PKA 109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define CLK_CRYPTO_NS_RNG 110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define HCLK_TRNG_NS 111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define CLK_TRNG_NS 112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define PCLK_OTPC_NS 113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define CLK_OTPC_NS_SBPI 114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define CLK_OTPC_NS_USR 115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define HCLK_NANDC 116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define NCLK_NANDC 117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define HCLK_SFC 118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define HCLK_SFC_XIP 119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define SCLK_SFC 120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define ACLK_EMMC 121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define HCLK_EMMC 122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define BCLK_EMMC 123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define CCLK_EMMC 124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define TCLK_EMMC 125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define ACLK_PIPE 126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define PCLK_PIPE 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define PCLK_PIPE_GRF 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define ACLK_PCIE20_MST 129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define ACLK_PCIE20_SLV 130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define ACLK_PCIE20_DBI 131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define PCLK_PCIE20 132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define CLK_PCIE20_AUX_NDFT 133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define CLK_PCIE20_AUX_DFT 134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define CLK_PCIE20_PIPE_DFT 135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define ACLK_PCIE30X1_MST 136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define ACLK_PCIE30X1_SLV 137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define ACLK_PCIE30X1_DBI 138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define PCLK_PCIE30X1 139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define CLK_PCIE30X1_AUX_NDFT 140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define CLK_PCIE30X1_AUX_DFT 141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define CLK_PCIE30X1_PIPE_DFT 142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define ACLK_PCIE30X2_MST 143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define ACLK_PCIE30X2_SLV 144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define ACLK_PCIE30X2_DBI 145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define PCLK_PCIE30X2 146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define CLK_PCIE30X2_AUX_NDFT 147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define CLK_PCIE30X2_AUX_DFT 148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define CLK_PCIE30X2_PIPE_DFT 149
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define ACLK_SATA0 150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define CLK_SATA0_PMALIVE 151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define CLK_SATA0_RXOOB 152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define CLK_SATA0_PIPE_NDFT 153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define CLK_SATA0_PIPE_DFT 154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define ACLK_SATA1 155
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define CLK_SATA1_PMALIVE 156
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define CLK_SATA1_RXOOB 157
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define CLK_SATA1_PIPE_NDFT 158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define CLK_SATA1_PIPE_DFT 159
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define ACLK_SATA2 160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define CLK_SATA2_PMALIVE 161
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define CLK_SATA2_RXOOB 162
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define CLK_SATA2_PIPE_NDFT 163
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define CLK_SATA2_PIPE_DFT 164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define ACLK_USB3OTG0 165
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define CLK_USB3OTG0_REF 166
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define CLK_USB3OTG0_SUSPEND 167
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define ACLK_USB3OTG1 168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define CLK_USB3OTG1_REF 169
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define CLK_USB3OTG1_SUSPEND 170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define CLK_XPCS_EEE 171
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define PCLK_XPCS 172
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define ACLK_PHP 173
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define HCLK_PHP 174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define PCLK_PHP 175
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define HCLK_SDMMC0 176
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define CLK_SDMMC0 177
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define HCLK_SDMMC1 178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define CLK_SDMMC1 179
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define ACLK_GMAC0 180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define PCLK_GMAC0 181
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define CLK_MAC0_2TOP 182
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define CLK_MAC0_OUT 183
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define CLK_MAC0_REFOUT 184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define CLK_GMAC0_PTP_REF 185
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define ACLK_USB 186
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define HCLK_USB 187
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define PCLK_USB 188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define HCLK_USB2HOST0 189
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define HCLK_USB2HOST0_ARB 190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define HCLK_USB2HOST1 191
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define HCLK_USB2HOST1_ARB 192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define HCLK_SDMMC2 193
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define CLK_SDMMC2 194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define ACLK_GMAC1 195
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define PCLK_GMAC1 196
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define CLK_MAC1_2TOP 197
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define CLK_MAC1_OUT 198
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define CLK_MAC1_REFOUT 199
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define CLK_GMAC1_PTP_REF 200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define ACLK_PERIMID 201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define HCLK_PERIMID 202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define ACLK_VI 203
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define HCLK_VI 204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define PCLK_VI 205
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define ACLK_VICAP 206
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define HCLK_VICAP 207
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define DCLK_VICAP 208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define ICLK_VICAP_G 209
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define ACLK_ISP 210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define HCLK_ISP 211
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define CLK_ISP 212
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define PCLK_CSI2HOST1 213
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define CLK_CIF_OUT 214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define CLK_CAM0_OUT 215
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define CLK_CAM1_OUT 216
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define ACLK_VO 217
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define HCLK_VO 218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define PCLK_VO 219
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define ACLK_VOP_PRE 220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define ACLK_VOP 221
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define HCLK_VOP 222
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define DCLK_VOP0 223
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define DCLK_VOP1 224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define DCLK_VOP2 225
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define CLK_VOP_PWM 226
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define ACLK_HDCP 227
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define HCLK_HDCP 228
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define PCLK_HDCP 229
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define PCLK_HDMI_HOST 230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define CLK_HDMI_SFR 231
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define PCLK_DSITX_0 232
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define PCLK_DSITX_1 233
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define PCLK_EDP_CTRL 234
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define CLK_EDP_200M 235
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define ACLK_VPU_PRE 236
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define HCLK_VPU_PRE 237
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define ACLK_VPU 238
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define HCLK_VPU 239
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define ACLK_RGA_PRE 240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define HCLK_RGA_PRE 241
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define PCLK_RGA_PRE 242
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define ACLK_RGA 243
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define HCLK_RGA 244
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define CLK_RGA_CORE 245
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define ACLK_IEP 246
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define HCLK_IEP 247
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define CLK_IEP_CORE 248
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define HCLK_EBC 249
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define DCLK_EBC 250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define ACLK_JDEC 251
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define HCLK_JDEC 252
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define ACLK_JENC 253
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define HCLK_JENC 254
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define PCLK_EINK 255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define HCLK_EINK 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define ACLK_RKVENC_PRE 257
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define HCLK_RKVENC_PRE 258
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define ACLK_RKVENC 259
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define HCLK_RKVENC 260
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define CLK_RKVENC_CORE 261
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define ACLK_RKVDEC_PRE 262
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define HCLK_RKVDEC_PRE 263
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define ACLK_RKVDEC 264
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define HCLK_RKVDEC 265
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define CLK_RKVDEC_CA 266
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define CLK_RKVDEC_CORE 267
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define CLK_RKVDEC_HEVC_CA 268
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define ACLK_BUS 269
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define PCLK_BUS 270
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define PCLK_TSADC 271
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define CLK_TSADC_TSEN 272
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define CLK_TSADC 273
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define PCLK_SARADC 274
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define CLK_SARADC 275
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define PCLK_SCR 276
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define PCLK_WDT_NS 277
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define TCLK_WDT_NS 278
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define ACLK_DMAC0 279
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define ACLK_DMAC1 280
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define ACLK_MCU 281
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define PCLK_INTMUX 282
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define PCLK_MAILBOX 283
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define PCLK_UART1 284
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define CLK_UART1_SRC 285
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define CLK_UART1_FRAC 286
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define SCLK_UART1 287
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define PCLK_UART2 288
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define CLK_UART2_SRC 289
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define CLK_UART2_FRAC 290
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define SCLK_UART2 291
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define PCLK_UART3 292
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define CLK_UART3_SRC 293
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define CLK_UART3_FRAC 294
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define SCLK_UART3 295
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define PCLK_UART4 296
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define CLK_UART4_SRC 297
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define CLK_UART4_FRAC 298
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define SCLK_UART4 299
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define PCLK_UART5 300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define CLK_UART5_SRC 301
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define CLK_UART5_FRAC 302
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define SCLK_UART5 303
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define PCLK_UART6 304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define CLK_UART6_SRC 305
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define CLK_UART6_FRAC 306
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define SCLK_UART6 307
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define PCLK_UART7 308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define CLK_UART7_SRC 309
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define CLK_UART7_FRAC 310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define SCLK_UART7 311
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define PCLK_UART8 312
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define CLK_UART8_SRC 313
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define CLK_UART8_FRAC 314
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define SCLK_UART8 315
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define PCLK_UART9 316
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define CLK_UART9_SRC 317
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define CLK_UART9_FRAC 318
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define SCLK_UART9 319
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define PCLK_CAN0 320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define CLK_CAN0 321
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define PCLK_CAN1 322
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define CLK_CAN1 323
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define PCLK_CAN2 324
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define CLK_CAN2 325
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define CLK_I2C 326
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define PCLK_I2C1 327
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define CLK_I2C1 328
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define PCLK_I2C2 329
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define CLK_I2C2 330
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define PCLK_I2C3 331
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define CLK_I2C3 332
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define PCLK_I2C4 333
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define CLK_I2C4 334
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define PCLK_I2C5 335
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define CLK_I2C5 336
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define PCLK_SPI0 337
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define CLK_SPI0 338
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define PCLK_SPI1 339
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define CLK_SPI1 340
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define PCLK_SPI2 341
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define CLK_SPI2 342
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define PCLK_SPI3 343
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define CLK_SPI3 344
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define PCLK_PWM1 345
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define CLK_PWM1 346
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define CLK_PWM1_CAPTURE 347
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define PCLK_PWM2 348
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define CLK_PWM2 349
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define CLK_PWM2_CAPTURE 350
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define PCLK_PWM3 351
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define CLK_PWM3 352
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define CLK_PWM3_CAPTURE 353
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define DBCLK_GPIO 354
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define PCLK_GPIO1 355
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define DBCLK_GPIO1 356
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define PCLK_GPIO2 357
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define DBCLK_GPIO2 358
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define PCLK_GPIO3 359
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define DBCLK_GPIO3 360
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define PCLK_GPIO4 361
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define DBCLK_GPIO4 362
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define OCC_SCAN_CLK_GPIO 363
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define PCLK_TIMER 364
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define CLK_TIMER0 365
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define CLK_TIMER1 366
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define CLK_TIMER2 367
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define CLK_TIMER3 368
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define CLK_TIMER4 369
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define CLK_TIMER5 370
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define ACLK_TOP_HIGH 371
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define ACLK_TOP_LOW 372
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define HCLK_TOP 373
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define PCLK_TOP 374
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define PCLK_PCIE30PHY 375
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define CLK_OPTC_ARB 376
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define PCLK_MIPICSIPHY 377
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define PCLK_MIPIDSIPHY0 378
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define PCLK_MIPIDSIPHY1 379
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define PCLK_PIPEPHY0 380
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define PCLK_PIPEPHY1 381
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define PCLK_PIPEPHY2 382
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define PCLK_CPU_BOOST 383
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define CLK_CPU_BOOST 384
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define PCLK_OTPPHY 385
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define SCLK_GMAC0 386
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define SCLK_GMAC0_RGMII_SPEED 387
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define SCLK_GMAC0_RMII_SPEED 388
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define SCLK_GMAC0_RX_TX 389
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define SCLK_GMAC1 390
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define SCLK_GMAC1_RGMII_SPEED 391
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define SCLK_GMAC1_RMII_SPEED 392
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define SCLK_GMAC1_RX_TX 393
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define SCLK_SDMMC0_DRV 394
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define SCLK_SDMMC0_SAMPLE 395
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define SCLK_SDMMC1_DRV 396
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define SCLK_SDMMC1_SAMPLE 397
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define SCLK_SDMMC2_DRV 398
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define SCLK_SDMMC2_SAMPLE 399
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define SCLK_EMMC_DRV 400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define SCLK_EMMC_SAMPLE 401
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define PCLK_EDPPHY_GRF 402
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define CLK_HDMI_CEC 403
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define CLK_I2S0_8CH_TX 404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define CLK_I2S0_8CH_RX 405
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define CLK_I2S1_8CH_TX 406
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define CLK_I2S1_8CH_RX 407
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define CLK_I2S2_2CH 408
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define CLK_I2S3_2CH_TX 409
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define CLK_I2S3_2CH_RX 410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define CPLL_500M 411
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define CPLL_250M 412
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define CPLL_125M 413
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define CPLL_62P5M 414
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define CPLL_50M 415
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define CPLL_25M 416
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define CPLL_100M 417
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define SCLK_DDRCLK 418
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define I2S1_MCLKOUT 419
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define I2S3_MCLKOUT 420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define I2S1_MCLK_RX_IOE 421
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define I2S1_MCLK_TX_IOE 422
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define I2S2_MCLK_IOE 423
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define I2S3_MCLK_IOE 424
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define PCLK_CORE_PVTM 450
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define CLK_NR_CLKS (PCLK_CORE_PVTM + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) /* pmu soft-reset indices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) /* pmucru_softrst_con0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define SRST_P_PDPMU_NIU 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define SRST_P_PMUCRU 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define SRST_P_PMUGRF 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define SRST_P_I2C0 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define SRST_I2C0 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define SRST_P_UART0 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define SRST_S_UART0 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define SRST_P_PWM0 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define SRST_PWM0 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define SRST_P_GPIO0 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define SRST_GPIO0 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define SRST_P_PMUPVTM 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define SRST_PMUPVTM 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) /* soft-reset indices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) /* cru_softrst_con0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define SRST_NCORERESET0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define SRST_NCORERESET1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define SRST_NCORERESET2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define SRST_NCORERESET3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define SRST_NCPUPORESET0 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define SRST_NCPUPORESET1 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define SRST_NCPUPORESET2 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define SRST_NCPUPORESET3 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define SRST_NSRESET 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define SRST_NSPORESET 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define SRST_NATRESET 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define SRST_NGICRESET 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define SRST_NPRESET 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define SRST_NPERIPHRESET 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) /* cru_softrst_con1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define SRST_A_CORE_NIU2DDR 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define SRST_A_CORE_NIU2BUS 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define SRST_P_DBG_NIU 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define SRST_P_DBG 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define SRST_P_DBG_DAPLITE 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define SRST_DAP 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define SRST_A_ADB400_CORE2GIC 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #define SRST_A_ADB400_GIC2CORE 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define SRST_P_CORE_GRF 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define SRST_P_CORE_PVTM 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define SRST_CORE_PVTM 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define SRST_CORE_PVTPLL 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) /* cru_softrst_con2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define SRST_GPU 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define SRST_A_GPU_NIU 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define SRST_P_GPU_NIU 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define SRST_P_GPU_PVTM 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define SRST_GPU_PVTM 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define SRST_GPU_PVTPLL 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define SRST_A_NPU_NIU 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define SRST_H_NPU_NIU 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define SRST_P_NPU_NIU 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define SRST_A_NPU 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define SRST_H_NPU 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define SRST_P_NPU_PVTM 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define SRST_NPU_PVTM 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define SRST_NPU_PVTPLL 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) /* cru_softrst_con3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define SRST_A_MSCH 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define SRST_HWFFC_CTRL 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define SRST_DDR_ALWAYSON 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #define SRST_A_DDRSPLIT 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #define SRST_DDRDFI_CTL 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #define SRST_A_DMA2DDR 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) /* cru_softrst_con4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #define SRST_A_PERIMID_NIU 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define SRST_H_PERIMID_NIU 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define SRST_A_GIC_AUDIO_NIU 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define SRST_H_GIC_AUDIO_NIU 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #define SRST_A_GIC600 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #define SRST_A_GIC600_DEBUG 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #define SRST_A_GICADB_CORE2GIC 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #define SRST_A_GICADB_GIC2CORE 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define SRST_A_SPINLOCK 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #define SRST_H_SDMMC_BUFFER 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define SRST_D_SDMMC_BUFFER 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define SRST_H_I2S0_8CH 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define SRST_H_I2S1_8CH 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define SRST_H_I2S2_2CH 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #define SRST_H_I2S3_2CH 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) /* cru_softrst_con5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #define SRST_M_I2S0_8CH_TX 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #define SRST_M_I2S0_8CH_RX 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #define SRST_M_I2S1_8CH_TX 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define SRST_M_I2S1_8CH_RX 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) #define SRST_M_I2S2_2CH 84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #define SRST_M_I2S3_2CH_TX 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #define SRST_M_I2S3_2CH_RX 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #define SRST_H_PDM 87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) #define SRST_M_PDM 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #define SRST_H_VAD 89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #define SRST_H_SPDIF_8CH 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #define SRST_M_SPDIF_8CH 91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #define SRST_H_AUDPWM 92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #define SRST_S_AUDPWM 93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) #define SRST_H_ACDCDIG 94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) #define SRST_ACDCDIG 95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) /* cru_softrst_con6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) #define SRST_A_SECURE_FLASH_NIU 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #define SRST_H_SECURE_FLASH_NIU 97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) #define SRST_A_CRYPTO_NS 103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #define SRST_H_CRYPTO_NS 104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) #define SRST_CRYPTO_NS_CORE 105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #define SRST_CRYPTO_NS_PKA 106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #define SRST_CRYPTO_NS_RNG 107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #define SRST_H_TRNG_NS 108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #define SRST_TRNG_NS 109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) /* cru_softrst_con7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #define SRST_H_NANDC 112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #define SRST_N_NANDC 113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #define SRST_H_SFC 114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #define SRST_H_SFC_XIP 115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #define SRST_S_SFC 116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #define SRST_A_EMMC 117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #define SRST_H_EMMC 118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) #define SRST_B_EMMC 119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) #define SRST_C_EMMC 120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) #define SRST_T_EMMC 121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) /* cru_softrst_con8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) #define SRST_A_PIPE_NIU 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #define SRST_P_PIPE_NIU 130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #define SRST_P_PIPE_GRF 133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) #define SRST_A_SATA0 134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) #define SRST_SATA0_PIPE 135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) #define SRST_SATA0_PMALIVE 136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) #define SRST_SATA0_RXOOB 137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #define SRST_A_SATA1 138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) #define SRST_SATA1_PIPE 139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) #define SRST_SATA1_PMALIVE 140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) #define SRST_SATA1_RXOOB 141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) /* cru_softrst_con9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) #define SRST_A_SATA2 144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) #define SRST_SATA2_PIPE 145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) #define SRST_SATA2_PMALIVE 146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) #define SRST_SATA2_RXOOB 147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) #define SRST_USB3OTG0 148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) #define SRST_USB3OTG1 149
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) #define SRST_XPCS 150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) #define SRST_XPCS_TX_DIV10 151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) #define SRST_XPCS_RX_DIV10 152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) #define SRST_XPCS_XGXS_RX 153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) /* cru_softrst_con10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) #define SRST_P_PCIE20 160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) #define SRST_PCIE20_POWERUP 161
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) #define SRST_MSTR_ARESET_PCIE20 162
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) #define SRST_SLV_ARESET_PCIE20 163
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) #define SRST_DBI_ARESET_PCIE20 164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) #define SRST_BRESET_PCIE20 165
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) #define SRST_PERST_PCIE20 166
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) #define SRST_CORE_RST_PCIE20 167
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) #define SRST_NSTICKY_RST_PCIE20 168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) #define SRST_STICKY_RST_PCIE20 169
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) #define SRST_PWR_RST_PCIE20 170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) /* cru_softrst_con11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) #define SRST_P_PCIE30X1 176
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) #define SRST_PCIE30X1_POWERUP 177
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) #define SRST_M_ARESET_PCIE30X1 178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) #define SRST_S_ARESET_PCIE30X1 179
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) #define SRST_D_ARESET_PCIE30X1 180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) #define SRST_BRESET_PCIE30X1 181
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) #define SRST_PERST_PCIE30X1 182
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) #define SRST_CORE_RST_PCIE30X1 183
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) #define SRST_NSTC_RST_PCIE30X1 184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) #define SRST_STC_RST_PCIE30X1 185
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) #define SRST_PWR_RST_PCIE30X1 186
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) /* cru_softrst_con12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) #define SRST_P_PCIE30X2 192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) #define SRST_PCIE30X2_POWERUP 193
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) #define SRST_M_ARESET_PCIE30X2 194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) #define SRST_S_ARESET_PCIE30X2 195
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) #define SRST_D_ARESET_PCIE30X2 196
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) #define SRST_BRESET_PCIE30X2 197
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) #define SRST_PERST_PCIE30X2 198
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) #define SRST_CORE_RST_PCIE30X2 199
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) #define SRST_NSTC_RST_PCIE30X2 200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) #define SRST_STC_RST_PCIE30X2 201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) #define SRST_PWR_RST_PCIE30X2 202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) /* cru_softrst_con13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) #define SRST_A_PHP_NIU 208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) #define SRST_H_PHP_NIU 209
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) #define SRST_P_PHP_NIU 210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) #define SRST_H_SDMMC0 211
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) #define SRST_SDMMC0 212
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) #define SRST_H_SDMMC1 213
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) #define SRST_SDMMC1 214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) #define SRST_A_GMAC0 215
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) #define SRST_GMAC0_TIMESTAMP 216
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) /* cru_softrst_con14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) #define SRST_A_USB_NIU 224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) #define SRST_H_USB_NIU 225
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) #define SRST_P_USB_NIU 226
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) #define SRST_P_USB_GRF 227
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) #define SRST_H_USB2HOST0 228
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) #define SRST_H_USB2HOST0_ARB 229
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) #define SRST_USB2HOST0_UTMI 230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) #define SRST_H_USB2HOST1 231
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) #define SRST_H_USB2HOST1_ARB 232
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) #define SRST_USB2HOST1_UTMI 233
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) #define SRST_H_SDMMC2 234
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) #define SRST_SDMMC2 235
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) #define SRST_A_GMAC1 236
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) #define SRST_GMAC1_TIMESTAMP 237
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) /* cru_softrst_con15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) #define SRST_A_VI_NIU 240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) #define SRST_H_VI_NIU 241
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) #define SRST_P_VI_NIU 242
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) #define SRST_A_VICAP 247
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) #define SRST_H_VICAP 248
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) #define SRST_D_VICAP 249
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) #define SRST_I_VICAP 250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) #define SRST_P_VICAP 251
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) #define SRST_H_ISP 252
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) #define SRST_ISP 253
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) #define SRST_P_CSI2HOST1 255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) /* cru_softrst_con16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) #define SRST_A_VO_NIU 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) #define SRST_H_VO_NIU 257
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) #define SRST_P_VO_NIU 258
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) #define SRST_A_VOP_NIU 259
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) #define SRST_A_VOP 260
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) #define SRST_H_VOP 261
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) #define SRST_VOP0 262
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) #define SRST_VOP1 263
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) #define SRST_VOP2 264
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) #define SRST_VOP_PWM 265
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) #define SRST_A_HDCP 266
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) #define SRST_H_HDCP 267
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) #define SRST_P_HDCP 268
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) #define SRST_P_HDMI_HOST 270
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) #define SRST_HDMI_HOST 271
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) /* cru_softrst_con17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) #define SRST_P_DSITX_0 272
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) #define SRST_P_DSITX_1 273
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) #define SRST_P_EDP_CTRL 274
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) #define SRST_EDP_24M 275
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) #define SRST_A_VPU_NIU 280
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) #define SRST_H_VPU_NIU 281
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) #define SRST_A_VPU 282
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) #define SRST_H_VPU 283
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) #define SRST_H_EINK 286
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) #define SRST_P_EINK 287
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) /* cru_softrst_con18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) #define SRST_A_RGA_NIU 288
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) #define SRST_H_RGA_NIU 289
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) #define SRST_P_RGA_NIU 290
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) #define SRST_A_RGA 292
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) #define SRST_H_RGA 293
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) #define SRST_RGA_CORE 294
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) #define SRST_A_IEP 295
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) #define SRST_H_IEP 296
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) #define SRST_IEP_CORE 297
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) #define SRST_H_EBC 298
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) #define SRST_D_EBC 299
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) #define SRST_A_JDEC 300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) #define SRST_H_JDEC 301
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) #define SRST_A_JENC 302
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) #define SRST_H_JENC 303
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) /* cru_softrst_con19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) #define SRST_A_VENC_NIU 304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) #define SRST_H_VENC_NIU 305
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) #define SRST_A_RKVENC 307
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) #define SRST_H_RKVENC 308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) #define SRST_RKVENC_CORE 309
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) /* cru_softrst_con20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) #define SRST_A_RKVDEC_NIU 320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) #define SRST_H_RKVDEC_NIU 321
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) #define SRST_A_RKVDEC 322
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) #define SRST_H_RKVDEC 323
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) #define SRST_RKVDEC_CA 324
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) #define SRST_RKVDEC_CORE 325
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) #define SRST_RKVDEC_HEVC_CA 326
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) /* cru_softrst_con21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) #define SRST_A_BUS_NIU 336
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) #define SRST_P_BUS_NIU 338
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) #define SRST_P_CAN0 340
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) #define SRST_CAN0 341
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) #define SRST_P_CAN1 342
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) #define SRST_CAN1 343
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) #define SRST_P_CAN2 344
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) #define SRST_CAN2 345
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) #define SRST_P_GPIO1 346
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) #define SRST_GPIO1 347
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) #define SRST_P_GPIO2 348
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) #define SRST_GPIO2 349
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) #define SRST_P_GPIO3 350
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) #define SRST_GPIO3 351
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) /* cru_softrst_con22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) #define SRST_P_GPIO4 352
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) #define SRST_GPIO4 353
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) #define SRST_P_I2C1 354
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) #define SRST_I2C1 355
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) #define SRST_P_I2C2 356
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) #define SRST_I2C2 357
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) #define SRST_P_I2C3 358
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) #define SRST_I2C3 359
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) #define SRST_P_I2C4 360
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) #define SRST_I2C4 361
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) #define SRST_P_I2C5 362
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) #define SRST_I2C5 363
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) #define SRST_P_OTPC_NS 364
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) #define SRST_OTPC_NS_SBPI 365
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) #define SRST_OTPC_NS_USR 366
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) /* cru_softrst_con23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) #define SRST_P_PWM1 368
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) #define SRST_PWM1 369
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) #define SRST_P_PWM2 370
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) #define SRST_PWM2 371
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) #define SRST_P_PWM3 372
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) #define SRST_PWM3 373
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) #define SRST_P_SPI0 374
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) #define SRST_SPI0 375
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) #define SRST_P_SPI1 376
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) #define SRST_SPI1 377
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) #define SRST_P_SPI2 378
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) #define SRST_SPI2 379
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) #define SRST_P_SPI3 380
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) #define SRST_SPI3 381
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) /* cru_softrst_con24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) #define SRST_P_SARADC 384
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) #define SRST_P_TSADC 385
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) #define SRST_TSADC 386
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) #define SRST_P_TIMER 387
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) #define SRST_TIMER0 388
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) #define SRST_TIMER1 389
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) #define SRST_TIMER2 390
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) #define SRST_TIMER3 391
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) #define SRST_TIMER4 392
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) #define SRST_TIMER5 393
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) #define SRST_P_UART1 394
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) #define SRST_S_UART1 395
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) /* cru_softrst_con25 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) #define SRST_P_UART2 400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) #define SRST_S_UART2 401
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) #define SRST_P_UART3 402
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) #define SRST_S_UART3 403
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) #define SRST_P_UART4 404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) #define SRST_S_UART4 405
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) #define SRST_P_UART5 406
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) #define SRST_S_UART5 407
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) #define SRST_P_UART6 408
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) #define SRST_S_UART6 409
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) #define SRST_P_UART7 410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) #define SRST_S_UART7 411
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) #define SRST_P_UART8 412
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) #define SRST_S_UART8 413
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) #define SRST_P_UART9 414
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) #define SRST_S_UART9 415
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) /* cru_softrst_con26 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) #define SRST_P_GRF 416
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) #define SRST_P_GRF_VCCIO12 417
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) #define SRST_P_GRF_VCCIO34 418
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) #define SRST_P_GRF_VCCIO567 419
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) #define SRST_P_SCR 420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) #define SRST_P_WDT_NS 421
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) #define SRST_T_WDT_NS 422
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) #define SRST_P_DFT2APB 423
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) #define SRST_A_MCU 426
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) #define SRST_P_INTMUX 427
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) #define SRST_P_MAILBOX 428
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) /* cru_softrst_con27 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) #define SRST_A_TOP_HIGH_NIU 432
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) #define SRST_A_TOP_LOW_NIU 433
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) #define SRST_H_TOP_NIU 434
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) #define SRST_P_TOP_NIU 435
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) #define SRST_P_TOP_CRU 438
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) #define SRST_P_DDRPHY 439
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) #define SRST_DDRPHY 440
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) #define SRST_P_MIPICSIPHY 442
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) #define SRST_P_MIPIDSIPHY0 443
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) #define SRST_P_MIPIDSIPHY1 444
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) #define SRST_P_PCIE30PHY 445
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) #define SRST_PCIE30PHY 446
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) #define SRST_P_PCIE30PHY_GRF 447
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) /* cru_softrst_con28 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) #define SRST_P_APB2ASB_LEFT 448
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) #define SRST_P_APB2ASB_BOTTOM 449
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) #define SRST_P_ASB2APB_LEFT 450
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) #define SRST_P_ASB2APB_BOTTOM 451
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) #define SRST_P_PIPEPHY0 452
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) #define SRST_PIPEPHY0 453
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) #define SRST_P_PIPEPHY1 454
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) #define SRST_PIPEPHY1 455
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) #define SRST_P_PIPEPHY2 456
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) #define SRST_PIPEPHY2 457
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) #define SRST_P_USB2PHY0_GRF 458
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) #define SRST_P_USB2PHY1_GRF 459
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) #define SRST_P_CPU_BOOST 460
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) #define SRST_CPU_BOOST 461
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) #define SRST_P_OTPPHY 462
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) #define SRST_OTPPHY 463
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) /* cru_softrst_con29 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) #define SRST_USB2PHY0_POR 464
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) #define SRST_USB2PHY0_USB3OTG0 465
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) #define SRST_USB2PHY0_USB3OTG1 466
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) #define SRST_USB2PHY1_POR 467
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) #define SRST_USB2PHY1_USB2HOST0 468
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) #define SRST_USB2PHY1_USB2HOST1 469
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) #define SRST_P_EDPPHY_GRF 470
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) #define SRST_TSADCPHY 471
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) #define SRST_GMAC0_DELAYLINE 472
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) #define SRST_GMAC1_DELAYLINE 473
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) #define SRST_OTPC_ARB 474
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) #define SRST_P_PIPEPHY0_GRF 475
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) #define SRST_P_PIPEPHY1_GRF 476
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) #define SRST_P_PIPEPHY2_GRF 477
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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