^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2016 Rockchip Electronics Co. Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Xing Zheng <zhengxing@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define RK3399_TWO_PLL_FOR_VOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /* core clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define PLL_APLLL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define PLL_APLLB 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define PLL_DPLL 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define PLL_CPLL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define PLL_GPLL 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PLL_NPLL 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PLL_VPLL 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define ARMCLKL 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define ARMCLKB 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* sclk gates (special clocks) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SCLK_I2SOUT_SRC 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SCLK_I2C1 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SCLK_I2C2 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SCLK_I2C3 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SCLK_I2C5 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SCLK_I2C6 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SCLK_I2C7 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SCLK_SPI0 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SCLK_SPI1 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SCLK_SPI2 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SCLK_SPI4 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SCLK_SPI5 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SCLK_SDMMC 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SCLK_SDIO 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SCLK_EMMC 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SCLK_TSADC 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SCLK_SARADC 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SCLK_UART0 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SCLK_UART1 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SCLK_UART2 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SCLK_UART3 84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SCLK_SPDIF_8CH 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SCLK_I2S0_8CH 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SCLK_I2S1_8CH 87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SCLK_I2S2_8CH 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SCLK_I2S_8CH_OUT 89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SCLK_TIMER00 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SCLK_TIMER01 91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SCLK_TIMER02 92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SCLK_TIMER03 93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SCLK_TIMER04 94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SCLK_TIMER05 95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SCLK_TIMER06 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SCLK_TIMER07 97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SCLK_TIMER08 98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SCLK_TIMER09 99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SCLK_TIMER10 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SCLK_TIMER11 101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SCLK_MACREF 102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SCLK_MAC_RX 103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SCLK_MAC_TX 104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SCLK_MAC 105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SCLK_MACREF_OUT 106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SCLK_VOP0_PWM 107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SCLK_VOP1_PWM 108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SCLK_RGA_CORE 109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SCLK_ISP0 110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SCLK_ISP1 111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SCLK_HDMI_CEC 112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SCLK_HDMI_SFR 113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SCLK_DP_CORE 114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SCLK_PVTM_CORE_L 115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SCLK_PVTM_CORE_B 116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SCLK_PVTM_GPU 117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SCLK_PVTM_DDR 118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SCLK_MIPIDPHY_REF 119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SCLK_MIPIDPHY_CFG 120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SCLK_HSICPHY 121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SCLK_USBPHY480M 122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SCLK_USB2PHY0_REF 123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SCLK_USB2PHY1_REF 124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SCLK_UPHY0_TCPDPHY_REF 125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SCLK_UPHY0_TCPDCORE 126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SCLK_UPHY1_TCPDPHY_REF 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SCLK_UPHY1_TCPDCORE 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SCLK_USB3OTG0_REF 129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SCLK_USB3OTG1_REF 130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SCLK_USB3OTG0_SUSPEND 131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SCLK_USB3OTG1_SUSPEND 132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SCLK_CRYPTO0 133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SCLK_CRYPTO1 134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SCLK_CCI_TRACE 135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SCLK_CS 136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define SCLK_CIF_OUT 137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define SCLK_PCIEPHY_REF 138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define SCLK_PCIE_CORE 139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SCLK_M0_PERILP 140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SCLK_M0_PERILP_DEC 141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define SCLK_CM0S 142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SCLK_DBG_NOC 143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SCLK_DBG_PD_CORE_B 144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SCLK_DBG_PD_CORE_L 145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SCLK_DFIMON0_TIMER 146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SCLK_DFIMON1_TIMER 147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define SCLK_INTMEM0 148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SCLK_INTMEM1 149
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define SCLK_INTMEM2 150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define SCLK_INTMEM3 151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define SCLK_INTMEM4 152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define SCLK_INTMEM5 153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SCLK_SDMMC_DRV 154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define SCLK_SDMMC_SAMPLE 155
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define SCLK_SDIO_DRV 156
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define SCLK_SDIO_SAMPLE 157
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define SCLK_VDU_CORE 158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define SCLK_VDU_CA 159
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define SCLK_PCIE_PM 160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define SCLK_SPDIF_REC_DPTX 161
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define SCLK_DPHY_PLL 162
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define SCLK_DPHY_TX0_CFG 163
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define SCLK_DPHY_TX1RX1_CFG 164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define SCLK_DPHY_RX0_CFG 165
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define SCLK_RMII_SRC 166
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define SCLK_PCIEPHY_REF100M 167
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define SCLK_USBPHY0_480M_SRC 168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define SCLK_USBPHY1_480M_SRC 169
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define SCLK_DDRC 170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define SCLK_TESTCLKOUT2 171
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define SCLK_UART0_SRC 172
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define SCLK_UART_SRC 173
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define SCLK_I2S0_DIV 174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define SCLK_I2S1_DIV 175
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define SCLK_I2S2_DIV 176
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define SCLK_SPDIF_DIV 177
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define SCLK_TESTCLKOUT1 179
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define SCLK_CIF_OUT_SRC 178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define DCLK_VOP0 180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define DCLK_VOP1 181
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define DCLK_VOP0_DIV 182
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define DCLK_VOP1_DIV 183
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define DCLK_M0_PERILP 184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define DCLK_VOP0_FRAC 185
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define DCLK_VOP1_FRAC 186
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define FCLK_CM0S 190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* aclk gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define ACLK_PERIHP 192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define ACLK_PERIHP_NOC 193
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define ACLK_PERILP0 194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define ACLK_PERILP0_NOC 195
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define ACLK_PERF_PCIE 196
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define ACLK_PCIE 197
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define ACLK_INTMEM 198
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define ACLK_TZMA 199
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define ACLK_DCF 200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define ACLK_CCI 201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define ACLK_CCI_NOC0 202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define ACLK_CCI_NOC1 203
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define ACLK_CCI_GRF 204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define ACLK_CENTER 205
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define ACLK_CENTER_MAIN_NOC 206
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define ACLK_CENTER_PERI_NOC 207
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define ACLK_GPU 208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define ACLK_PERF_GPU 209
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define ACLK_GPU_GRF 210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define ACLK_DMAC0_PERILP 211
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define ACLK_DMAC1_PERILP 212
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define ACLK_GMAC 213
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define ACLK_GMAC_NOC 214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define ACLK_PERF_GMAC 215
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define ACLK_VOP0_NOC 216
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define ACLK_VOP0 217
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define ACLK_VOP1_NOC 218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define ACLK_VOP1 219
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define ACLK_RGA 220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define ACLK_RGA_NOC 221
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define ACLK_HDCP 222
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define ACLK_HDCP_NOC 223
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define ACLK_HDCP22 224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define ACLK_IEP 225
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define ACLK_IEP_NOC 226
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define ACLK_VIO 227
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define ACLK_VIO_NOC 228
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define ACLK_ISP0 229
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define ACLK_ISP1 230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define ACLK_ISP0_NOC 231
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define ACLK_ISP1_NOC 232
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define ACLK_ISP0_WRAPPER 233
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define ACLK_ISP1_WRAPPER 234
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define ACLK_VCODEC 235
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define ACLK_VCODEC_NOC 236
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define ACLK_VDU 237
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define ACLK_VDU_NOC 238
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define ACLK_PERI 239
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define ACLK_EMMC 240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define ACLK_EMMC_CORE 241
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define ACLK_EMMC_NOC 242
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define ACLK_EMMC_GRF 243
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define ACLK_USB3 244
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define ACLK_USB3_NOC 245
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define ACLK_USB3OTG0 246
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define ACLK_USB3OTG1 247
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define ACLK_USB3_RKSOC_AXI_PERF 248
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define ACLK_USB3_GRF 249
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define ACLK_GIC 250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define ACLK_GIC_NOC 251
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define ACLK_GIC_ADB400_CORE_L_2_GIC 252
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define ACLK_GIC_ADB400_CORE_B_2_GIC 253
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define ACLK_GIC_ADB400_GIC_2_CORE_L 254
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define ACLK_GIC_ADB400_GIC_2_CORE_B 255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define ACLK_CORE_ADB400_CORE_L_2_CCI500 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define ACLK_CORE_ADB400_CORE_B_2_CCI500 257
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define ACLK_ADB400M_PD_CORE_L 258
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define ACLK_ADB400M_PD_CORE_B 259
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define ACLK_PERF_CORE_L 260
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define ACLK_PERF_CORE_B 261
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define ACLK_GIC_PRE 262
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define ACLK_VOP0_PRE 263
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define ACLK_VOP1_PRE 264
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* pclk gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define PCLK_PERIHP 320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define PCLK_PERIHP_NOC 321
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define PCLK_PERILP0 322
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define PCLK_PERILP1 323
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define PCLK_PERILP1_NOC 324
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define PCLK_PERILP_SGRF 325
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define PCLK_PERIHP_GRF 326
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define PCLK_PCIE 327
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define PCLK_SGRF 328
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define PCLK_INTR_ARB 329
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define PCLK_CENTER_MAIN_NOC 330
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define PCLK_CIC 331
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define PCLK_COREDBG_B 332
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define PCLK_COREDBG_L 333
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define PCLK_DBG_CXCS_PD_CORE_B 334
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define PCLK_DCF 335
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define PCLK_GPIO2 336
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define PCLK_GPIO3 337
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define PCLK_GPIO4 338
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define PCLK_GRF 339
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define PCLK_HSICPHY 340
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define PCLK_I2C1 341
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define PCLK_I2C2 342
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define PCLK_I2C3 343
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define PCLK_I2C5 344
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define PCLK_I2C6 345
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define PCLK_I2C7 346
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define PCLK_SPI0 347
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define PCLK_SPI1 348
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define PCLK_SPI2 349
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define PCLK_SPI4 350
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define PCLK_SPI5 351
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define PCLK_UART0 352
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define PCLK_UART1 353
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define PCLK_UART2 354
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define PCLK_UART3 355
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define PCLK_TSADC 356
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define PCLK_SARADC 357
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define PCLK_GMAC 358
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define PCLK_GMAC_NOC 359
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define PCLK_TIMER0 360
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define PCLK_TIMER1 361
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define PCLK_EDP 362
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define PCLK_EDP_NOC 363
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define PCLK_EDP_CTRL 364
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define PCLK_VIO 365
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define PCLK_VIO_NOC 366
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define PCLK_VIO_GRF 367
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define PCLK_MIPI_DSI0 368
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define PCLK_MIPI_DSI1 369
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define PCLK_HDCP 370
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define PCLK_HDCP_NOC 371
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define PCLK_HDMI_CTRL 372
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define PCLK_DP_CTRL 373
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define PCLK_HDCP22 374
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define PCLK_GASKET 375
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define PCLK_DDR 376
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define PCLK_DDR_MON 377
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define PCLK_DDR_SGRF 378
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define PCLK_ISP1_WRAPPER 379
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define PCLK_WDT 380
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define PCLK_EFUSE1024NS 381
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define PCLK_EFUSE1024S 382
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define PCLK_PMU_INTR_ARB 383
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define PCLK_MAILBOX0 384
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define PCLK_USBPHY_MUX_G 385
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define PCLK_UPHY0_TCPHY_G 386
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define PCLK_UPHY0_TCPD_G 387
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define PCLK_UPHY1_TCPHY_G 388
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define PCLK_UPHY1_TCPD_G 389
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define PCLK_ALIVE 390
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /* hclk gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define HCLK_PERIHP 448
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define HCLK_PERILP0 449
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define HCLK_PERILP1 450
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define HCLK_PERILP0_NOC 451
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define HCLK_PERILP1_NOC 452
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define HCLK_M0_PERILP 453
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define HCLK_M0_PERILP_NOC 454
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define HCLK_AHB1TOM 455
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define HCLK_HOST0 456
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define HCLK_HOST0_ARB 457
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define HCLK_HOST1 458
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define HCLK_HOST1_ARB 459
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define HCLK_HSIC 460
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define HCLK_SD 461
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define HCLK_SDMMC 462
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define HCLK_SDMMC_NOC 463
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define HCLK_M_CRYPTO0 464
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define HCLK_M_CRYPTO1 465
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define HCLK_S_CRYPTO0 466
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define HCLK_S_CRYPTO1 467
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define HCLK_I2S0_8CH 468
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define HCLK_I2S1_8CH 469
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define HCLK_I2S2_8CH 470
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define HCLK_SPDIF 471
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define HCLK_VOP0_NOC 472
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define HCLK_VOP0 473
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define HCLK_VOP1_NOC 474
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define HCLK_VOP1 475
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define HCLK_ROM 476
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define HCLK_IEP 477
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define HCLK_IEP_NOC 478
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define HCLK_ISP0 479
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define HCLK_ISP1 480
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define HCLK_ISP0_NOC 481
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define HCLK_ISP1_NOC 482
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define HCLK_ISP0_WRAPPER 483
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define HCLK_ISP1_WRAPPER 484
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define HCLK_RGA 485
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define HCLK_RGA_NOC 486
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define HCLK_HDCP 487
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define HCLK_HDCP_NOC 488
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define HCLK_HDCP22 489
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define HCLK_VCODEC 490
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define HCLK_VCODEC_NOC 491
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define HCLK_VDU 492
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define HCLK_VDU_NOC 493
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define HCLK_SDIO 494
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define HCLK_SDIO_NOC 495
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define HCLK_SDIOAUDIO_NOC 496
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define CLK_NR_CLKS (HCLK_SDIOAUDIO_NOC + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /* pmu-clocks indices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define PLL_PPLL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define SCLK_32K_SUSPEND_PMU 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define SCLK_SPI3_PMU 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define SCLK_TIMER12_PMU 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define SCLK_TIMER13_PMU 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define SCLK_UART4_PMU 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define SCLK_PVTM_PMU 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define SCLK_WIFI_PMU 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define SCLK_I2C0_PMU 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define SCLK_I2C4_PMU 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define SCLK_I2C8_PMU 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define SCLK_UART4_SRC 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define PCLK_SRC_PMU 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define PCLK_PMU 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define PCLK_PMUGRF_PMU 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define PCLK_INTMEM1_PMU 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define PCLK_GPIO0_PMU 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define PCLK_GPIO1_PMU 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define PCLK_SGRF_PMU 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define PCLK_NOC_PMU 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define PCLK_I2C0_PMU 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define PCLK_I2C4_PMU 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define PCLK_I2C8_PMU 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define PCLK_RKPWM_PMU 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define PCLK_SPI3_PMU 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define PCLK_TIMER_PMU 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define PCLK_MAILBOX_PMU 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define PCLK_UART4_PMU 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define PCLK_WDT_M0_PMU 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define FCLK_CM0S_SRC_PMU 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define FCLK_CM0S_PMU 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define SCLK_CM0S_PMU 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define HCLK_CM0S_PMU 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define DCLK_CM0S_PMU 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define PCLK_INTR_ARB_PMU 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define HCLK_NOC_PMU 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define CLKPMU_NR_CLKS (HCLK_NOC_PMU + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /* soft-reset indices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /* cru_softrst_con0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define SRST_CORE_L0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define SRST_CORE_B0 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define SRST_CORE_PO_L0 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define SRST_CORE_PO_B0 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define SRST_L2_L 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define SRST_L2_B 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define SRST_ADB_L 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define SRST_ADB_B 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define SRST_A_CCI 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define SRST_A_CCIM0_NOC 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define SRST_A_CCIM1_NOC 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define SRST_DBG_NOC 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) /* cru_softrst_con1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define SRST_CORE_L0_T 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define SRST_CORE_L1 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define SRST_CORE_L2 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define SRST_CORE_L3 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define SRST_CORE_PO_L0_T 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define SRST_CORE_PO_L1 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define SRST_CORE_PO_L2 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define SRST_CORE_PO_L3 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define SRST_A_ADB400_GIC2COREL 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define SRST_A_ADB400_COREL2GIC 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define SRST_P_DBG_L 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define SRST_L2_L_T 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define SRST_ADB_L_T 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define SRST_A_RKPERF_L 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define SRST_PVTM_CORE_L 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /* cru_softrst_con2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define SRST_CORE_B0_T 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define SRST_CORE_B1 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define SRST_CORE_PO_B0_T 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define SRST_CORE_PO_B1 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define SRST_A_ADB400_GIC2COREB 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define SRST_A_ADB400_COREB2GIC 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define SRST_P_DBG_B 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define SRST_L2_B_T 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define SRST_ADB_B_T 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define SRST_A_RKPERF_B 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define SRST_PVTM_CORE_B 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) /* cru_softrst_con3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define SRST_A_CCI_T 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define SRST_A_CCIM0_NOC_T 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define SRST_A_CCIM1_NOC_T 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define SRST_A_ADB400M_PD_CORE_B_T 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define SRST_A_ADB400M_PD_CORE_L_T 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define SRST_DBG_NOC_T 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define SRST_DBG_CXCS 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define SRST_CCI_TRACE 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define SRST_P_CCI_GRF 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) /* cru_softrst_con4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define SRST_A_CENTER_MAIN_NOC 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define SRST_A_CENTER_PERI_NOC 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define SRST_P_CENTER_MAIN 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define SRST_P_DDRMON 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define SRST_P_CIC 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define SRST_P_CENTER_SGRF 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define SRST_DDR0_MSCH 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define SRST_DDRCFG0_MSCH 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define SRST_DDR0 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define SRST_DDRPHY0 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define SRST_DDR1_MSCH 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define SRST_DDRCFG1_MSCH 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define SRST_DDR1 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define SRST_DDRPHY1 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define SRST_DDR_CIC 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define SRST_PVTM_DDR 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /* cru_softrst_con5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define SRST_A_VCODEC_NOC 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define SRST_A_VCODEC 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define SRST_H_VCODEC_NOC 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define SRST_H_VCODEC 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define SRST_A_VDU_NOC 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define SRST_A_VDU 89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define SRST_H_VDU_NOC 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define SRST_H_VDU 91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define SRST_VDU_CORE 92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define SRST_VDU_CA 93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) /* cru_softrst_con6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define SRST_A_IEP_NOC 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define SRST_A_VOP_IEP 97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define SRST_A_IEP 98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define SRST_H_IEP_NOC 99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define SRST_H_IEP 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define SRST_A_RGA_NOC 102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define SRST_A_RGA 103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define SRST_H_RGA_NOC 104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define SRST_H_RGA 105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define SRST_RGA_CORE 106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define SRST_EMMC_NOC 108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define SRST_EMMC 109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define SRST_EMMC_GRF 110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) /* cru_softrst_con7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define SRST_A_PERIHP_NOC 112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define SRST_P_PERIHP_GRF 113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define SRST_H_PERIHP_NOC 114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define SRST_USBHOST0 115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define SRST_HOSTC0_AUX 116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define SRST_HOST0_ARB 117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define SRST_USBHOST1 118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define SRST_HOSTC1_AUX 119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define SRST_HOST1_ARB 120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define SRST_SDIO0 121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define SRST_SDMMC 122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define SRST_HSIC 123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define SRST_HSIC_AUX 124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define SRST_AHB1TOM 125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define SRST_P_PERIHP_NOC 126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define SRST_HSICPHY 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) /* cru_softrst_con8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define SRST_A_PCIE 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define SRST_P_PCIE 129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define SRST_PCIE_CORE 130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define SRST_PCIE_MGMT 131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define SRST_PCIE_MGMT_STICKY 132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define SRST_PCIE_PIPE 133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define SRST_PCIE_PM 134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define SRST_PCIEPHY 135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define SRST_A_GMAC_NOC 136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define SRST_A_GMAC 137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define SRST_P_GMAC_NOC 138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define SRST_P_GMAC_GRF 140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define SRST_HSICPHY_POR 142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define SRST_HSICPHY_UTMI 143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) /* cru_softrst_con9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define SRST_USB2PHY0_POR 144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define SRST_USB2PHY0_UTMI_PORT0 145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #define SRST_USB2PHY0_UTMI_PORT1 146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define SRST_USB2PHY0_EHCIPHY 147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define SRST_UPHY0_PIPE_L00 148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define SRST_UPHY0 149
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define SRST_UPHY0_TCPDPWRUP 150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define SRST_USB2PHY1_POR 152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define SRST_USB2PHY1_UTMI_PORT0 153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define SRST_USB2PHY1_UTMI_PORT1 154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define SRST_USB2PHY1_EHCIPHY 155
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define SRST_UPHY1_PIPE_L00 156
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define SRST_UPHY1 157
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define SRST_UPHY1_TCPDPWRUP 158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) /* cru_softrst_con10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define SRST_A_PERILP0_NOC 160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define SRST_A_DCF 161
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define SRST_GIC500 162
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define SRST_DMAC0_PERILP0 163
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define SRST_DMAC1_PERILP0 164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define SRST_TZMA 165
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define SRST_INTMEM 166
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define SRST_ADB400_MST0 167
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define SRST_ADB400_MST1 168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define SRST_ADB400_SLV0 169
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define SRST_ADB400_SLV1 170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define SRST_H_PERILP0 171
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #define SRST_H_PERILP0_NOC 172
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #define SRST_ROM 173
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #define SRST_CRYPTO_S 174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define SRST_CRYPTO_M 175
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) /* cru_softrst_con11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define SRST_P_DCF 176
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define SRST_CM0S_NOC 177
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define SRST_CM0S 178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #define SRST_CM0S_DBG 179
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #define SRST_CM0S_PO 180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #define SRST_CRYPTO 181
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #define SRST_P_PERILP1_SGRF 182
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define SRST_P_PERILP1_GRF 183
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #define SRST_CRYPTO1_S 184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define SRST_CRYPTO1_M 185
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define SRST_CRYPTO1 186
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define SRST_GIC_NOC 188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define SRST_SD_NOC 189
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #define SRST_SDIOAUDIO_BRG 190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) /* cru_softrst_con12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #define SRST_H_PERILP1 192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #define SRST_H_PERILP1_NOC 193
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #define SRST_H_I2S0_8CH 194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define SRST_H_I2S1_8CH 195
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) #define SRST_H_I2S2_8CH 196
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #define SRST_H_SPDIF_8CH 197
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #define SRST_P_PERILP1_NOC 198
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #define SRST_P_EFUSE_1024 199
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) #define SRST_P_EFUSE_1024S 200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #define SRST_P_I2C0 201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #define SRST_P_I2C1 202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #define SRST_P_I2C2 203
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #define SRST_P_I2C3 204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #define SRST_P_I2C4 205
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) #define SRST_P_I2C5 206
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) #define SRST_P_MAILBOX0 207
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) /* cru_softrst_con13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) #define SRST_P_UART0 208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #define SRST_P_UART1 209
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) #define SRST_P_UART2 210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #define SRST_P_UART3 211
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) #define SRST_P_SARADC 212
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #define SRST_P_TSADC 213
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #define SRST_P_SPI0 214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #define SRST_P_SPI1 215
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #define SRST_P_SPI2 216
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) #define SRST_P_SPI4 217
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #define SRST_P_SPI5 218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #define SRST_SPI0 219
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #define SRST_SPI1 220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #define SRST_SPI2 221
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #define SRST_SPI4 222
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #define SRST_SPI5 223
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) /* cru_softrst_con14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) #define SRST_I2S0_8CH 224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) #define SRST_I2S1_8CH 225
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) #define SRST_I2S2_8CH 226
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #define SRST_SPDIF_8CH 227
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) #define SRST_UART0 228
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) #define SRST_UART1 229
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #define SRST_UART2 230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #define SRST_UART3 231
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) #define SRST_TSADC 232
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) #define SRST_I2C0 233
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) #define SRST_I2C1 234
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) #define SRST_I2C2 235
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #define SRST_I2C3 236
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) #define SRST_I2C4 237
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) #define SRST_I2C5 238
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) #define SRST_SDIOAUDIO_NOC 239
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) /* cru_softrst_con15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) #define SRST_A_VIO_NOC 240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) #define SRST_A_HDCP_NOC 241
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) #define SRST_A_HDCP 242
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) #define SRST_H_HDCP_NOC 243
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) #define SRST_H_HDCP 244
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) #define SRST_P_HDCP_NOC 245
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) #define SRST_P_HDCP 246
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) #define SRST_P_HDMI_CTRL 247
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) #define SRST_P_DP_CTRL 248
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) #define SRST_S_DP_CTRL 249
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) #define SRST_C_DP_CTRL 250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) #define SRST_P_MIPI_DSI0 251
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) #define SRST_P_MIPI_DSI1 252
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) #define SRST_DP_CORE 253
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) #define SRST_DP_I2S 254
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) /* cru_softrst_con16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) #define SRST_GASKET 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) #define SRST_VIO_GRF 258
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) #define SRST_DPTX_SPDIF_REC 259
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) #define SRST_HDMI_CTRL 260
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) #define SRST_HDCP_CTRL 261
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) #define SRST_A_ISP0_NOC 262
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) #define SRST_A_ISP1_NOC 263
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) #define SRST_H_ISP0_NOC 266
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) #define SRST_H_ISP1_NOC 267
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) #define SRST_H_ISP0 268
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) #define SRST_H_ISP1 269
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) #define SRST_ISP0 270
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) #define SRST_ISP1 271
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) /* cru_softrst_con17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) #define SRST_A_VOP0_NOC 272
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) #define SRST_A_VOP1_NOC 273
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) #define SRST_A_VOP0 274
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) #define SRST_A_VOP1 275
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) #define SRST_H_VOP0_NOC 276
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) #define SRST_H_VOP1_NOC 277
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) #define SRST_H_VOP0 278
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) #define SRST_H_VOP1 279
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) #define SRST_D_VOP0 280
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) #define SRST_D_VOP1 281
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) #define SRST_VOP0_PWM 282
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) #define SRST_VOP1_PWM 283
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) #define SRST_P_EDP_NOC 284
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) #define SRST_P_EDP_CTRL 285
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) /* cru_softrst_con18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) #define SRST_A_GPU 288
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) #define SRST_A_GPU_NOC 289
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) #define SRST_A_GPU_GRF 290
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) #define SRST_PVTM_GPU 291
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) #define SRST_A_USB3_NOC 292
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) #define SRST_A_USB3_OTG0 293
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) #define SRST_A_USB3_OTG1 294
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) #define SRST_A_USB3_GRF 295
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) #define SRST_PMU 296
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) /* cru_softrst_con19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) #define SRST_P_TIMER0_5 304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) #define SRST_TIMER0 305
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) #define SRST_TIMER1 306
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) #define SRST_TIMER2 307
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) #define SRST_TIMER3 308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) #define SRST_TIMER4 309
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) #define SRST_TIMER5 310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) #define SRST_P_TIMER6_11 311
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) #define SRST_TIMER6 312
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) #define SRST_TIMER7 313
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) #define SRST_TIMER8 314
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) #define SRST_TIMER9 315
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) #define SRST_TIMER10 316
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) #define SRST_TIMER11 317
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) #define SRST_P_INTR_ARB_PMU 318
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) #define SRST_P_ALIVE_SGRF 319
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) /* cru_softrst_con20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) #define SRST_P_GPIO2 320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) #define SRST_P_GPIO3 321
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) #define SRST_P_GPIO4 322
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) #define SRST_P_GRF 323
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) #define SRST_P_ALIVE_NOC 324
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) #define SRST_P_WDT0 325
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) #define SRST_P_WDT1 326
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) #define SRST_P_INTR_ARB 327
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) #define SRST_P_UPHY0_DPTX 328
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) #define SRST_P_UPHY0_APB 330
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) #define SRST_P_UPHY0_TCPHY 332
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) #define SRST_P_UPHY1_TCPHY 333
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) #define SRST_P_UPHY0_TCPDCTRL 334
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) #define SRST_P_UPHY1_TCPDCTRL 335
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) /* pmu soft-reset indices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) /* pmu_cru_softrst_con0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) #define SRST_P_NOC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) #define SRST_P_INTMEM 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) #define SRST_H_CM0S 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) #define SRST_H_CM0S_NOC 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) #define SRST_DBG_CM0S 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) #define SRST_PO_CM0S 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) #define SRST_P_SPI3 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) #define SRST_SPI3 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) #define SRST_P_TIMER_0_1 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) #define SRST_P_TIMER_0 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) #define SRST_P_TIMER_1 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) #define SRST_P_UART4 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) #define SRST_UART4 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) #define SRST_P_WDT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) /* pmu_cru_softrst_con1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) #define SRST_P_I2C6 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) #define SRST_P_I2C7 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) #define SRST_P_I2C8 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) #define SRST_P_MAILBOX 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) #define SRST_P_RKPWM 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) #define SRST_P_PMUGRF 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) #define SRST_P_SGRF 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) #define SRST_P_GPIO0 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) #define SRST_P_GPIO1 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) #define SRST_P_CRU 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) #define SRST_P_INTR 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) #define SRST_PVTM 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) #define SRST_I2C6 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) #define SRST_I2C7 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) #define SRST_I2C8 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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