Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2016 Rockchip Electronics Co. Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Author: Elaine <zhangqing@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3328_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #define _DT_BINDINGS_CLK_ROCKCHIP_RK3328_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) /* core clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define PLL_APLL		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define PLL_DPLL		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define PLL_CPLL		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define PLL_GPLL		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define PLL_NPLL		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define ARMCLK			6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) /* sclk gates (special clocks) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define SCLK_RTC32K		30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define SCLK_SDMMC_EXT		31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define SCLK_SPI		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define SCLK_SDMMC		33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define SCLK_SDIO		34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define SCLK_EMMC		35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define SCLK_TSADC		36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define SCLK_SARADC		37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define SCLK_UART0		38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define SCLK_UART1		39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define SCLK_UART2		40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define SCLK_I2S0		41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define SCLK_I2S1		42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define SCLK_I2S2		43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define SCLK_I2S1_OUT		44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define SCLK_I2S2_OUT		45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define SCLK_SPDIF		46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define SCLK_TIMER0		47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define SCLK_TIMER1		48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define SCLK_TIMER2		49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define SCLK_TIMER3		50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define SCLK_TIMER4		51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define SCLK_TIMER5		52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define SCLK_WIFI		53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define SCLK_CIF_OUT		54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define SCLK_I2C0		55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define SCLK_I2C1		56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define SCLK_I2C2		57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define SCLK_I2C3		58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define SCLK_CRYPTO		59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define SCLK_PWM		60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define SCLK_PDM		61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define SCLK_EFUSE		62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define SCLK_OTP		63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define SCLK_DDRCLK		64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define SCLK_VDEC_CABAC		65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define SCLK_VDEC_CORE		66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define SCLK_VENC_DSP		67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define SCLK_VENC_CORE		68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define SCLK_RGA		69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define SCLK_HDMI_SFC		70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define SCLK_HDMI_CEC		71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define SCLK_USB3_REF		72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define SCLK_USB3_SUSPEND	73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define SCLK_SDMMC_DRV		74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define SCLK_SDIO_DRV		75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define SCLK_EMMC_DRV		76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define SCLK_SDMMC_EXT_DRV	77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define SCLK_SDMMC_SAMPLE	78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define SCLK_SDIO_SAMPLE	79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define SCLK_EMMC_SAMPLE	80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define SCLK_SDMMC_EXT_SAMPLE	81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define SCLK_VOP		82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define SCLK_MAC2PHY_RXTX	83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define SCLK_MAC2PHY_SRC	84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define SCLK_MAC2PHY_REF	85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define SCLK_MAC2PHY_OUT	86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define SCLK_MAC2IO_RX		87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define SCLK_MAC2IO_TX		88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define SCLK_MAC2IO_REFOUT	89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define SCLK_MAC2IO_REF		90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define SCLK_MAC2IO_OUT		91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define SCLK_TSP		92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define SCLK_HSADC_TSP		93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define SCLK_USB3PHY_REF	94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define SCLK_REF_USB3OTG	95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define SCLK_USB3OTG_REF	96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define SCLK_USB3OTG_SUSPEND	97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define SCLK_REF_USB3OTG_SRC	98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define SCLK_MAC2IO_SRC		99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define SCLK_MAC2IO		100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define SCLK_MAC2PHY		101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define SCLK_MAC2IO_EXT		102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) /* dclk gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define DCLK_LCDC		120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define DCLK_HDMIPHY		121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define HDMIPHY			122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define USB480M			123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define DCLK_LCDC_SRC		124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* aclk gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define ACLK_AXISRAM		130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define ACLK_VOP_PRE		131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define ACLK_USB3OTG		132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define ACLK_RGA_PRE		133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define ACLK_DMAC		134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define ACLK_GPU		135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define ACLK_BUS_PRE		136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define ACLK_PERI_PRE		137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define ACLK_RKVDEC_PRE		138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define ACLK_RKVDEC		139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define ACLK_RKVENC		140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define ACLK_VPU_PRE		141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define ACLK_VIO_PRE		142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define ACLK_VPU		143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define ACLK_VIO		144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define ACLK_VOP		145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define ACLK_GMAC		146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define ACLK_H265		147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define ACLK_H264		148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define ACLK_MAC2PHY		149
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define ACLK_MAC2IO		150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define ACLK_DCF		151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define ACLK_TSP		152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define ACLK_PERI		153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define ACLK_RGA		154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define ACLK_IEP		155
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define ACLK_CIF		156
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define ACLK_HDCP		157
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* pclk gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define PCLK_GPIO0		200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define PCLK_GPIO1		201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define PCLK_GPIO2		202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define PCLK_GPIO3		203
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define PCLK_GRF		204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define PCLK_I2C0		205
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define PCLK_I2C1		206
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define PCLK_I2C2		207
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define PCLK_I2C3		208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define PCLK_SPI		209
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define PCLK_UART0		210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define PCLK_UART1		211
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define PCLK_UART2		212
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define PCLK_TSADC		213
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define PCLK_PWM		214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define PCLK_TIMER		215
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define PCLK_BUS_PRE		216
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define PCLK_PERI_PRE		217
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define PCLK_HDMI_CTRL		218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define PCLK_HDMI_PHY		219
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define PCLK_GMAC		220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define PCLK_H265		221
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define PCLK_MAC2PHY		222
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define PCLK_MAC2IO		223
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define PCLK_USB3PHY_OTG	224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define PCLK_USB3PHY_PIPE	225
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define PCLK_USB3_GRF		226
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define PCLK_USB2_GRF		227
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define PCLK_HDMIPHY		228
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define PCLK_DDR		229
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define PCLK_PERI		230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define PCLK_HDMI		231
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define PCLK_HDCP		232
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define PCLK_DCF		233
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define PCLK_SARADC		234
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define PCLK_ACODECPHY		235
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define PCLK_WDT		236
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* hclk gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define HCLK_PERI		308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define HCLK_TSP		309
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define HCLK_GMAC		310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define HCLK_I2S0_8CH		311
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define HCLK_I2S1_8CH		312
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define HCLK_I2S2_2CH		313
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define HCLK_SPDIF_8CH		314
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define HCLK_VOP		315
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define HCLK_NANDC		316
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define HCLK_SDMMC		317
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define HCLK_SDIO		318
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define HCLK_EMMC		319
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define HCLK_SDMMC_EXT		320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define HCLK_RKVDEC_PRE		321
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define HCLK_RKVDEC		322
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define HCLK_RKVENC		323
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define HCLK_VPU_PRE		324
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define HCLK_VIO_PRE		325
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define HCLK_VPU		326
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define HCLK_BUS_PRE		328
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define HCLK_PERI_PRE		329
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define HCLK_H264		330
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define HCLK_CIF		331
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define HCLK_OTG_PMU		332
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define HCLK_OTG		333
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define HCLK_HOST0		334
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define HCLK_HOST0_ARB		335
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define HCLK_CRYPTO_MST		336
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define HCLK_CRYPTO_SLV		337
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define HCLK_PDM		338
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define HCLK_IEP		339
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define HCLK_RGA		340
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define HCLK_HDCP		341
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define CLK_NR_CLKS		(HCLK_HDCP + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* soft-reset indices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define SRST_CORE0_PO		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define SRST_CORE1_PO		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define SRST_CORE2_PO		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define SRST_CORE3_PO		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define SRST_CORE0		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define SRST_CORE1		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define SRST_CORE2		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define SRST_CORE3		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define SRST_CORE0_DBG		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define SRST_CORE1_DBG		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define SRST_CORE2_DBG		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define SRST_CORE3_DBG		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define SRST_TOPDBG		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define SRST_CORE_NIU		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define SRST_STRC_A		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define SRST_L2C		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define SRST_A53_GIC		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define SRST_DAP		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define SRST_PMU_P		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define SRST_EFUSE		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define SRST_BUSSYS_H		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define SRST_BUSSYS_P		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define SRST_SPDIF		25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define SRST_INTMEM		26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define SRST_ROM		27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define SRST_GPIO0		28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define SRST_GPIO1		29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define SRST_GPIO2		30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define SRST_GPIO3		31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define SRST_I2S0		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define SRST_I2S1		33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define SRST_I2S2		34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define SRST_I2S0_H		35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define SRST_I2S1_H		36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define SRST_I2S2_H		37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define SRST_UART0		38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define SRST_UART1		39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define SRST_UART2		40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define SRST_UART0_P		41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define SRST_UART1_P		42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define SRST_UART2_P		43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define SRST_I2C0		44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define SRST_I2C1		45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define SRST_I2C2		46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define SRST_I2C3		47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define SRST_I2C0_P		48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define SRST_I2C1_P		49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define SRST_I2C2_P		50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define SRST_I2C3_P		51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define SRST_EFUSE_SE_P		52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define SRST_EFUSE_NS_P		53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define SRST_PWM0		54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define SRST_PWM0_P		55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define SRST_DMA		56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define SRST_TSP_A		57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define SRST_TSP_H		58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define SRST_TSP		59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define SRST_TSP_HSADC		60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define SRST_DCF_A		61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define SRST_DCF_P		62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define SRST_SCR		64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define SRST_SPI		65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define SRST_TSADC		66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define SRST_TSADC_P		67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define SRST_CRYPTO		68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define SRST_SGRF		69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define SRST_GRF		70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define SRST_USB_GRF		71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define SRST_TIMER_6CH_P	72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define SRST_TIMER0		73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define SRST_TIMER1		74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define SRST_TIMER2		75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define SRST_TIMER3		76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define SRST_TIMER4		77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define SRST_TIMER5		78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define SRST_USB3GRF		79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define SRST_PHYNIU		80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define SRST_HDMIPHY		81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define SRST_VDAC		82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define SRST_ACODEC_p		83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define SRST_SARADC		85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define SRST_SARADC_P		86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define SRST_GRF_DDR		87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define SRST_DFIMON		88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define SRST_MSCH		89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define SRST_DDRMSCH		91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define SRST_DDRCTRL		92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define SRST_DDRCTRL_P		93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define SRST_DDRPHY		94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define SRST_DDRPHY_P		95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define SRST_GMAC_NIU_A		96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define SRST_GMAC_NIU_P		97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define SRST_GMAC2PHY_A		98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define SRST_GMAC2IO_A		99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define SRST_MACPHY		100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define SRST_OTP_PHY		101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define SRST_GPU_A		102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define SRST_GPU_NIU_A		103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define SRST_SDMMCEXT		104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define SRST_PERIPH_NIU_A	105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define SRST_PERIHP_NIU_H	106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define SRST_PERIHP_P		107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define SRST_PERIPHSYS_H	108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define SRST_MMC0		109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define SRST_SDIO		110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define SRST_EMMC		111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define SRST_USB2OTG_H		112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define SRST_USB2OTG		113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define SRST_USB2OTG_ADP	114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define SRST_USB2HOST_H		115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define SRST_USB2HOST_ARB	116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define SRST_USB2HOST_AUX	117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define SRST_USB2HOST_EHCIPHY	118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define SRST_USB2HOST_UTMI	119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define SRST_USB3OTG		120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define SRST_USBPOR		121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define SRST_USB2OTG_UTMI	122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define SRST_USB2HOST_PHY_UTMI	123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define SRST_USB3OTG_UTMI	124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define SRST_USB3PHY_U2		125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define SRST_USB3PHY_U3		126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define SRST_USB3PHY_PIPE	127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define SRST_VIO_A		128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define SRST_VIO_BUS_H		129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define SRST_VIO_H2P_H		130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define SRST_VIO_ARBI_H		131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define SRST_VOP_NIU_A		132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define SRST_VOP_A		133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define SRST_VOP_H		134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define SRST_VOP_D		135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define SRST_RGA		136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define SRST_RGA_NIU_A		137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define SRST_RGA_A		138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define SRST_RGA_H		139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define SRST_IEP_A		140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define SRST_IEP_H		141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define SRST_HDMI		142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define SRST_HDMI_P		143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define SRST_HDCP_A		144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define SRST_HDCP		145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define SRST_HDCP_H		146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define SRST_CIF_A		147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define SRST_CIF_H		148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define SRST_CIF_P		149
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define SRST_OTP_P		150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define SRST_OTP_SBPI		151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define SRST_OTP_USER		152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define SRST_DDRCTRL_A		153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define SRST_DDRSTDY_P		154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define SRST_DDRSTDY		155
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define SRST_PDM_H		156
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define SRST_PDM		157
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define SRST_USB3PHY_OTG_P	158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define SRST_USB3PHY_PIPE_P	159
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define SRST_VCODEC_A		160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define SRST_VCODEC_NIU_A	161
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define SRST_VCODEC_H		162
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define SRST_VCODEC_NIU_H	163
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define SRST_VDEC_A		164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define SRST_VDEC_NIU_A		165
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define SRST_VDEC_H		166
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define SRST_VDEC_NIU_H		167
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define SRST_VDEC_CORE		168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define SRST_VDEC_CABAC		169
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define SRST_DDRPHYDIV		175
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define SRST_RKVENC_NIU_A	176
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define SRST_RKVENC_NIU_H	177
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define SRST_RKVENC_H265_A	178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define SRST_RKVENC_H265_P	179
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define SRST_RKVENC_H265_CORE	180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define SRST_RKVENC_H265_DSP	181
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define SRST_RKVENC_H264_A	182
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define SRST_RKVENC_H264_H	183
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define SRST_RKVENC_INTMEM	184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #endif