Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2019 Rockchip Electronics Co. Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Author: Finley Xiao <finley.xiao@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3308_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #define _DT_BINDINGS_CLK_ROCKCHIP_RK3308_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) /* core clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define PLL_APLL		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define PLL_DPLL		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define PLL_VPLL0		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define PLL_VPLL1		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define ARMCLK			5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) /* sclk (special clocks) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define USB480M			14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define SCLK_RTC32K		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define SCLK_PVTM_CORE		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define SCLK_UART0		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define SCLK_UART1		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define SCLK_UART2		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define SCLK_UART3		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define SCLK_UART4		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define SCLK_I2C0		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define SCLK_I2C1		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define SCLK_I2C2		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define SCLK_I2C3		25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define SCLK_PWM0		26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define SCLK_SPI0		27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define SCLK_SPI1		28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define SCLK_SPI2		29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define SCLK_TIMER0		30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define SCLK_TIMER1		31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define SCLK_TIMER2		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define SCLK_TIMER3		33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define SCLK_TIMER4		34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define SCLK_TIMER5		35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define SCLK_TSADC		36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define SCLK_SARADC		37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define SCLK_OTP		38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define SCLK_OTP_USR		39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define SCLK_CPU_BOOST		40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define SCLK_CRYPTO		41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define SCLK_CRYPTO_APK		42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define SCLK_NANDC_DIV		43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define SCLK_NANDC_DIV50	44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define SCLK_NANDC		45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define SCLK_SDMMC_DIV		46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define SCLK_SDMMC_DIV50	47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define SCLK_SDMMC		48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define SCLK_SDMMC_DRV		49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define SCLK_SDMMC_SAMPLE	50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define SCLK_SDIO_DIV		51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define SCLK_SDIO_DIV50		52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define SCLK_SDIO		53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define SCLK_SDIO_DRV		54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define SCLK_SDIO_SAMPLE	55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define SCLK_EMMC_DIV		56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define SCLK_EMMC_DIV50		57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define SCLK_EMMC		58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define SCLK_EMMC_DRV		59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define SCLK_EMMC_SAMPLE	60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define SCLK_SFC		61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define SCLK_OTG_ADP		62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define SCLK_MAC_SRC		63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define SCLK_MAC		64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define SCLK_MAC_REF		65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define SCLK_MAC_RX_TX		66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define SCLK_MAC_RMII		67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define SCLK_DDR_MON_TIMER	68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define SCLK_DDR_MON		69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define SCLK_DDRCLK		70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define SCLK_PMU		71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define SCLK_USBPHY_REF		72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define SCLK_WIFI		73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define SCLK_PVTM_PMU		74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define SCLK_PDM		75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define SCLK_I2S0_8CH_TX	76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define SCLK_I2S0_8CH_TX_OUT	77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define SCLK_I2S0_8CH_RX	78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define SCLK_I2S0_8CH_RX_OUT	79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define SCLK_I2S1_8CH_TX	80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define SCLK_I2S1_8CH_TX_OUT	81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define SCLK_I2S1_8CH_RX	82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define SCLK_I2S1_8CH_RX_OUT	83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define SCLK_I2S2_8CH_TX	84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define SCLK_I2S2_8CH_TX_OUT	85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define SCLK_I2S2_8CH_RX	86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define SCLK_I2S2_8CH_RX_OUT	87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define SCLK_I2S3_8CH_TX	88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define SCLK_I2S3_8CH_TX_OUT	89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define SCLK_I2S3_8CH_RX	90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define SCLK_I2S3_8CH_RX_OUT	91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define SCLK_I2S0_2CH		92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define SCLK_I2S0_2CH_OUT	93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define SCLK_I2S1_2CH		94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define SCLK_I2S1_2CH_OUT	95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SCLK_SPDIF_TX_DIV	96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SCLK_SPDIF_TX_DIV50	97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define SCLK_SPDIF_TX		98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SCLK_SPDIF_RX_DIV	99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SCLK_SPDIF_RX_DIV50	100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SCLK_SPDIF_RX		101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SCLK_I2S0_8CH_TX_MUX	102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SCLK_I2S0_8CH_RX_MUX	103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define SCLK_I2S1_8CH_TX_MUX	104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SCLK_I2S1_8CH_RX_MUX	105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define SCLK_I2S2_8CH_TX_MUX	106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define SCLK_I2S2_8CH_RX_MUX	107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define SCLK_I2S3_8CH_TX_MUX	108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define SCLK_I2S3_8CH_RX_MUX	109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SCLK_I2S0_8CH_TX_SRC	110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define SCLK_I2S0_8CH_RX_SRC	111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define SCLK_I2S1_8CH_TX_SRC	112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define SCLK_I2S1_8CH_RX_SRC	113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define SCLK_I2S2_8CH_TX_SRC	114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define SCLK_I2S2_8CH_RX_SRC	115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define SCLK_I2S3_8CH_TX_SRC	116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define SCLK_I2S3_8CH_RX_SRC	117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define SCLK_I2S0_2CH_SRC	118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define SCLK_I2S1_2CH_SRC	119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define SCLK_PWM1		120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define SCLK_PWM2		121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define SCLK_OWIRE		122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* dclk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define DCLK_VOP		125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* aclk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define ACLK_BUS_SRC		130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define ACLK_BUS		131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define ACLK_PERI_SRC		132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define ACLK_PERI		133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define ACLK_MAC		134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define ACLK_CRYPTO		135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define ACLK_VOP		136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define ACLK_GIC		137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define ACLK_DMAC0		138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define ACLK_DMAC1		139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* hclk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define HCLK_BUS		150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define HCLK_PERI		151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define HCLK_AUDIO		152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define HCLK_NANDC		153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define HCLK_SDMMC		154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define HCLK_SDIO		155
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define HCLK_EMMC		156
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define HCLK_SFC		157
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define HCLK_OTG		158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define HCLK_HOST		159
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define HCLK_HOST_ARB		160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define HCLK_PDM		161
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define HCLK_SPDIFTX		162
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define HCLK_SPDIFRX		163
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define HCLK_I2S0_8CH		164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define HCLK_I2S1_8CH		165
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define HCLK_I2S2_8CH		166
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define HCLK_I2S3_8CH		167
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define HCLK_I2S0_2CH		168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define HCLK_I2S1_2CH		169
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define HCLK_VAD		170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define HCLK_CRYPTO		171
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define HCLK_VOP		172
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* pclk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define PCLK_BUS		190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define PCLK_DDR		191
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define PCLK_PERI		192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define PCLK_PMU		193
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define PCLK_AUDIO		194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define PCLK_MAC		195
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define PCLK_ACODEC		196
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define PCLK_UART0		197
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define PCLK_UART1		198
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define PCLK_UART2		199
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define PCLK_UART3		200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define PCLK_UART4		201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define PCLK_I2C0		202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define PCLK_I2C1		203
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define PCLK_I2C2		204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define PCLK_I2C3		205
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define PCLK_PWM0		206
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define PCLK_SPI0		207
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define PCLK_SPI1		208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define PCLK_SPI2		209
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define PCLK_SARADC		210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define PCLK_TSADC		211
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define PCLK_TIMER		212
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define PCLK_OTP_NS		213
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define PCLK_WDT		214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define PCLK_GPIO0		215
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define PCLK_GPIO1		216
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define PCLK_GPIO2		217
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define PCLK_GPIO3		218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define PCLK_GPIO4		219
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define PCLK_SGRF		220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define PCLK_GRF		221
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define PCLK_USBSD_DET		222
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define PCLK_DDR_UPCTL		223
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define PCLK_DDR_MON		224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define PCLK_DDRPHY		225
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define PCLK_DDR_STDBY		226
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define PCLK_USB_GRF		227
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define PCLK_CRU		228
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define PCLK_OTP_PHY		229
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define PCLK_CPU_BOOST		230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define PCLK_PWM1		231
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define PCLK_PWM2		232
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define PCLK_CAN		233
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define PCLK_OWIRE		234
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define CLK_NR_CLKS		(PCLK_OWIRE + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* soft-reset indices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* cru_softrst_con0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define SRST_CORE0_PO		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define SRST_CORE1_PO		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define SRST_CORE2_PO		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define SRST_CORE3_PO		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define SRST_CORE0		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define SRST_CORE1		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define SRST_CORE2		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define SRST_CORE3		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define SRST_CORE0_DBG		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define SRST_CORE1_DBG		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define SRST_CORE2_DBG		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define SRST_CORE3_DBG		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define SRST_TOPDBG		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define SRST_CORE_NOC		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define SRST_STRC_A		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define SRST_L2C		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* cru_softrst_con1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define SRST_DAP		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define SRST_CORE_PVTM		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define SRST_CORE_PRF		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define SRST_CORE_GRF		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define SRST_DDRUPCTL		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define SRST_DDRUPCTL_P		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define SRST_MSCH		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define SRST_DDRMON_P		25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define SRST_DDRSTDBY_P		26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define SRST_DDRSTDBY		27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define SRST_DDRPHY		28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define SRST_DDRPHY_DIV		29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define SRST_DDRPHY_P		30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* cru_softrst_con2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define SRST_BUS_NIU_H		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define SRST_USB_NIU_P		33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define SRST_CRYPTO_A		34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define SRST_CRYPTO_H		35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define SRST_CRYPTO		36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define SRST_CRYPTO_APK		37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define SRST_VOP_A		38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define SRST_VOP_H		39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define SRST_VOP_D		40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define SRST_INTMEM_A		41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define SRST_ROM_H		42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define SRST_GIC_A		43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define SRST_UART0_P		44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define SRST_UART0		45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define SRST_UART1_P		46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define SRST_UART1		47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /* cru_softrst_con3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define SRST_UART2_P		48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define SRST_UART2		49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define SRST_UART3_P		50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define SRST_UART3		51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define SRST_UART4_P		52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define SRST_UART4		53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define SRST_I2C0_P		54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define SRST_I2C0		55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define SRST_I2C1_P		56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define SRST_I2C1		57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define SRST_I2C2_P		58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define SRST_I2C2		59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define SRST_I2C3_P		60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define SRST_I2C3		61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define SRST_PWM0_P		62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define SRST_PWM0		63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* cru_softrst_con4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define SRST_SPI0_P		64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define SRST_SPI0		65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define SRST_SPI1_P		66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define SRST_SPI1		67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define SRST_SPI2_P		68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define SRST_SPI2		69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define SRST_SARADC_P		70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define SRST_TSADC_P		71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define SRST_TSADC		72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define SRST_TIMER0_P		73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define SRST_TIMER0		74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define SRST_TIMER1		75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define SRST_TIMER2		76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define SRST_TIMER3		77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define SRST_TIMER4		78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define SRST_TIMER5		79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* cru_softrst_con5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define SRST_OTP_NS_P		80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define SRST_OTP_NS_SBPI	81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define SRST_OTP_NS_USR		82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define SRST_OTP_PHY_P		83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define SRST_OTP_PHY		84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define SRST_GPIO0_P		86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define SRST_GPIO1_P		87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define SRST_GPIO2_P		88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define SRST_GPIO3_P		89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define SRST_GPIO4_P		90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define SRST_GRF_P		91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define SRST_USBSD_DET_P	92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define SRST_PMU		93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define SRST_PMU_PVTM		94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define SRST_USB_GRF_P		95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /* cru_softrst_con6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define SRST_CPU_BOOST		96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define SRST_CPU_BOOST_P	97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define SRST_PWM1_P		98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define SRST_PWM1		99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define SRST_PWM2_P		100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define SRST_PWM2		101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define SRST_PERI_NIU_A		104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define SRST_PERI_NIU_H		105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define SRST_PERI_NIU_p		106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define SRST_USB2OTG_H		107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define SRST_USB2OTG		108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define SRST_USB2OTG_ADP	109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define SRST_USB2HOST_H		110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define SRST_USB2HOST_ARB_H	111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) /* cru_softrst_con7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define SRST_USB2HOST_AUX_H	112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define SRST_USB2HOST_EHCI	113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define SRST_USB2HOST		114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define SRST_USBPHYPOR		115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define SRST_UTMI0		116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define SRST_UTMI1		117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define SRST_SDIO_H		118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define SRST_EMMC_H		119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define SRST_SFC_H		120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define SRST_SFC		121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define SRST_SD_H		122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define SRST_NANDC_H		123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define SRST_NANDC_N		124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define SRST_MAC_A		125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define SRST_CAN_P		126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define SRST_OWIRE_P		127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /* cru_softrst_con8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define SRST_AUDIO_NIU_H	128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define SRST_AUDIO_NIU_P	129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define SRST_PDM_H		130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define SRST_PDM_M		131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define SRST_SPDIFTX_H		132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define SRST_SPDIFTX_M		133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define SRST_SPDIFRX_H		134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define SRST_SPDIFRX_M		135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define SRST_I2S0_8CH_H		136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define SRST_I2S0_8CH_TX_M	137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define SRST_I2S0_8CH_RX_M	138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define SRST_I2S1_8CH_H		139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define SRST_I2S1_8CH_TX_M	140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define SRST_I2S1_8CH_RX_M	141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define SRST_I2S2_8CH_H		142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define SRST_I2S2_8CH_TX_M	143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /* cru_softrst_con9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define SRST_I2S2_8CH_RX_M	144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define SRST_I2S3_8CH_H		145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define SRST_I2S3_8CH_TX_M	146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define SRST_I2S3_8CH_RX_M	147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define SRST_I2S0_2CH_H		148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define SRST_I2S0_2CH_M		149
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define SRST_I2S1_2CH_H		150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define SRST_I2S1_2CH_M		151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define SRST_VAD_H		152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define SRST_ACODEC_P		153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #endif