Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2014 MundoReader S.L.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Author: Heiko Stuebner <heiko@sntech.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3288_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #define _DT_BINDINGS_CLK_ROCKCHIP_RK3288_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) /* core clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define PLL_APLL		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define PLL_DPLL		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define PLL_CPLL		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define PLL_GPLL		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define PLL_NPLL		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define ARMCLK			6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) /* sclk gates (special clocks) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define SCLK_GPU		64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define SCLK_SPI0		65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define SCLK_SPI1		66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define SCLK_SPI2		67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define SCLK_SDMMC		68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define SCLK_SDIO0		69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define SCLK_SDIO1		70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define SCLK_EMMC		71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define SCLK_TSADC		72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define SCLK_SARADC		73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define SCLK_PS2C		74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define SCLK_NANDC0		75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define SCLK_NANDC1		76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define SCLK_UART0		77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define SCLK_UART1		78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define SCLK_UART2		79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define SCLK_UART3		80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define SCLK_UART4		81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define SCLK_I2S0		82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define SCLK_SPDIF		83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define SCLK_SPDIF8CH		84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define SCLK_TIMER0		85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define SCLK_TIMER1		86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define SCLK_TIMER2		87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define SCLK_TIMER3		88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define SCLK_TIMER4		89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define SCLK_TIMER5		90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define SCLK_TIMER6		91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define SCLK_HSADC		92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define SCLK_OTGPHY0		93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define SCLK_OTGPHY1		94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define SCLK_OTGPHY2		95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define SCLK_OTG_ADP		96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define SCLK_HSICPHY480M	97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define SCLK_HSICPHY12M		98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define SCLK_MACREF		99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define SCLK_LCDC_PWM0		100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define SCLK_LCDC_PWM1		101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define SCLK_MAC_RX		102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define SCLK_MAC_TX		103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define SCLK_EDP_24M		104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define SCLK_EDP		105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define SCLK_RGA		106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define SCLK_ISP		107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define SCLK_ISP_JPE		108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define SCLK_HDMI_HDCP		109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define SCLK_HDMI_CEC		110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define SCLK_HEVC_CABAC		111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define SCLK_HEVC_CORE		112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define SCLK_I2S0_OUT		113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define SCLK_SDMMC_DRV		114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define SCLK_SDIO0_DRV		115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define SCLK_SDIO1_DRV		116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define SCLK_EMMC_DRV		117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define SCLK_SDMMC_SAMPLE	118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define SCLK_SDIO0_SAMPLE	119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define SCLK_SDIO1_SAMPLE	120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define SCLK_EMMC_SAMPLE	121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define SCLK_USBPHY480M_SRC	122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define SCLK_PVTM_CORE		123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define SCLK_PVTM_GPU		124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define SCLK_CRYPTO		125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define SCLK_MIPIDSI_24M	126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define SCLK_VIP_OUT		127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define SCLK_MAC		151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define SCLK_MACREF_OUT		152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define DCLK_VOP0		190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define DCLK_VOP1		191
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) /* aclk gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define ACLK_GPU		192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define ACLK_DMAC1		193
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define ACLK_DMAC2		194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define ACLK_MMU		195
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define ACLK_GMAC		196
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define ACLK_VOP0		197
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define ACLK_VOP1		198
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define ACLK_CRYPTO		199
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define ACLK_RGA		200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define ACLK_RGA_NIU		201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define ACLK_IEP		202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define ACLK_VIO0_NIU		203
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define ACLK_VIP		204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define ACLK_ISP		205
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define ACLK_VIO1_NIU		206
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define ACLK_HEVC		207
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define ACLK_VCODEC		208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define ACLK_CPU		209
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define ACLK_PERI		210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* pclk gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define PCLK_GPIO0		320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define PCLK_GPIO1		321
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define PCLK_GPIO2		322
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define PCLK_GPIO3		323
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define PCLK_GPIO4		324
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define PCLK_GPIO5		325
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define PCLK_GPIO6		326
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define PCLK_GPIO7		327
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define PCLK_GPIO8		328
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define PCLK_GRF		329
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define PCLK_SGRF		330
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define PCLK_PMU		331
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define PCLK_I2C0		332
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define PCLK_I2C1		333
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define PCLK_I2C2		334
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define PCLK_I2C3		335
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define PCLK_I2C4		336
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define PCLK_I2C5		337
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define PCLK_SPI0		338
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define PCLK_SPI1		339
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define PCLK_SPI2		340
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define PCLK_UART0		341
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define PCLK_UART1		342
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define PCLK_UART2		343
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define PCLK_UART3		344
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define PCLK_UART4		345
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define PCLK_TSADC		346
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define PCLK_SARADC		347
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define PCLK_SIM		348
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define PCLK_GMAC		349
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define PCLK_PWM		350
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define PCLK_RKPWM		351
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define PCLK_PS2C		352
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define PCLK_TIMER		353
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define PCLK_TZPC		354
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define PCLK_EDP_CTRL		355
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define PCLK_MIPI_DSI0		356
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define PCLK_MIPI_DSI1		357
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define PCLK_MIPI_CSI		358
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define PCLK_LVDS_PHY		359
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define PCLK_HDMI_CTRL		360
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define PCLK_VIO2_H2P		361
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define PCLK_CPU		362
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define PCLK_PERI		363
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define PCLK_DDRUPCTL0		364
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define PCLK_PUBL0		365
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define PCLK_DDRUPCTL1		366
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define PCLK_PUBL1		367
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define PCLK_WDT		368
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define PCLK_EFUSE256		369
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define PCLK_EFUSE1024		370
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define PCLK_ISP_IN		371
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define PCLK_VIP		372
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define PCLK_VIP_IN		373
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define PCLK_PD_ALIVE		374
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define PCLK_PD_PMU		375
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* hclk gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define HCLK_GPS		448
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define HCLK_OTG0		449
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define HCLK_USBHOST0		450
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define HCLK_USBHOST1		451
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define HCLK_HSIC		452
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define HCLK_NANDC0		453
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define HCLK_NANDC1		454
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define HCLK_TSP		455
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define HCLK_SDMMC		456
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define HCLK_SDIO0		457
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define HCLK_SDIO1		458
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define HCLK_EMMC		459
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define HCLK_HSADC		460
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define HCLK_CRYPTO		461
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define HCLK_I2S0		462
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define HCLK_SPDIF		463
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define HCLK_SPDIF8CH		464
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define HCLK_VOP0		465
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define HCLK_VOP1		466
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define HCLK_ROM		467
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define HCLK_IEP		468
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define HCLK_ISP		469
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define HCLK_RGA		470
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define HCLK_VIO_AHB_ARBI	471
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define HCLK_VIO_NIU		472
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define HCLK_VIP		473
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define HCLK_VIO2_H2P		474
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define HCLK_HEVC		475
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define HCLK_VCODEC		476
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define HCLK_CPU		477
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define HCLK_PERI		478
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define CLK_NR_CLKS		(HCLK_PERI + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* soft-reset indices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define SRST_CORE0		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define SRST_CORE1		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define SRST_CORE2		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define SRST_CORE3		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define SRST_CORE0_PO		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define SRST_CORE1_PO		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define SRST_CORE2_PO		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define SRST_CORE3_PO		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define SRST_PDCORE_STRSYS	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define SRST_PDBUS_STRSYS	9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define SRST_L2C		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define SRST_TOPDBG		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define SRST_CORE0_DBG		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define SRST_CORE1_DBG		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define SRST_CORE2_DBG		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define SRST_CORE3_DBG		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define SRST_PDBUG_AHB_ARBITOR	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define SRST_EFUSE256		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define SRST_DMAC1		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define SRST_INTMEM		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define SRST_ROM		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define SRST_SPDIF8CH		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define SRST_TIMER		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define SRST_I2S0		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define SRST_SPDIF		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define SRST_TIMER0		25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define SRST_TIMER1		26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define SRST_TIMER2		27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define SRST_TIMER3		28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define SRST_TIMER4		29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define SRST_TIMER5		30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define SRST_EFUSE		31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define SRST_GPIO0		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define SRST_GPIO1		33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define SRST_GPIO2		34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define SRST_GPIO3		35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define SRST_GPIO4		36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define SRST_GPIO5		37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define SRST_GPIO6		38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define SRST_GPIO7		39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define SRST_GPIO8		40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define SRST_I2C0		42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define SRST_I2C1		43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define SRST_I2C2		44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define SRST_I2C3		45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define SRST_I2C4		46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define SRST_I2C5		47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define SRST_DWPWM		48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define SRST_MMC_PERI		49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define SRST_PERIPH_MMU		50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define SRST_DAP		51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define SRST_DAP_SYS		52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define SRST_TPIU		53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define SRST_PMU_APB		54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define SRST_GRF		55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define SRST_PMU		56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define SRST_PERIPH_AXI		57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define SRST_PERIPH_AHB		58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define SRST_PERIPH_APB		59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define SRST_PERIPH_NIU		60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define SRST_PDPERI_AHB_ARBI	61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define SRST_EMEM		62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define SRST_USB_PERI		63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define SRST_DMAC2		64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define SRST_MAC		66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define SRST_GPS		67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define SRST_RKPWM		69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define SRST_CCP		71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define SRST_USBHOST0		72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define SRST_HSIC		73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define SRST_HSIC_AUX		74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define SRST_HSIC_PHY		75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define SRST_HSADC		76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define SRST_NANDC0		77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define SRST_NANDC1		78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define SRST_TZPC		80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define SRST_SPI0		83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define SRST_SPI1		84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define SRST_SPI2		85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define SRST_SARADC		87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define SRST_PDALIVE_NIU	88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define SRST_PDPMU_INTMEM	89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define SRST_PDPMU_NIU		90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define SRST_SGRF		91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define SRST_VIO_ARBI		96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define SRST_RGA_NIU		97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define SRST_VIO0_NIU_AXI	98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define SRST_VIO_NIU_AHB	99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define SRST_LCDC0_AXI		100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define SRST_LCDC0_AHB		101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define SRST_LCDC0_DCLK		102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define SRST_VIO1_NIU_AXI	103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define SRST_VIP		104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define SRST_RGA_CORE		105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define SRST_IEP_AXI		106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define SRST_IEP_AHB		107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define SRST_RGA_AXI		108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define SRST_RGA_AHB		109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define SRST_ISP		110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define SRST_EDP		111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define SRST_VCODEC_AXI		112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define SRST_VCODEC_AHB		113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define SRST_VIO_H2P		114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define SRST_MIPIDSI0		115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define SRST_MIPIDSI1		116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define SRST_MIPICSI		117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define SRST_LVDS_PHY		118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define SRST_LVDS_CON		119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define SRST_GPU		120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define SRST_HDMI		121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define SRST_CORE_PVTM		124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define SRST_GPU_PVTM		125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define SRST_MMC0		128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define SRST_SDIO0		129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define SRST_SDIO1		130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define SRST_EMMC		131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define SRST_USBOTG_AHB		132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define SRST_USBOTG_PHY		133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define SRST_USBOTG_CON		134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define SRST_USBHOST0_AHB	135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define SRST_USBHOST0_PHY	136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define SRST_USBHOST0_CON	137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define SRST_USBHOST1_AHB	138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define SRST_USBHOST1_PHY	139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define SRST_USBHOST1_CON	140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define SRST_USB_ADP		141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define SRST_ACC_EFUSE		142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define SRST_CORESIGHT		144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define SRST_PD_CORE_AHB_NOC	145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define SRST_PD_CORE_APB_NOC	146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define SRST_PD_CORE_MP_AXI	147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define SRST_GIC		148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define SRST_LCDC_PWM0		149
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define SRST_LCDC_PWM1		150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define SRST_VIO0_H2P_BRG	151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define SRST_VIO1_H2P_BRG	152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define SRST_RGA_H2P_BRG	153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define SRST_HEVC		154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define SRST_TSADC		159
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define SRST_DDRPHY0		160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define SRST_DDRPHY0_APB	161
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define SRST_DDRCTRL0		162
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define SRST_DDRCTRL0_APB	163
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define SRST_DDRPHY0_CTRL	164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define SRST_DDRPHY1		165
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define SRST_DDRPHY1_APB	166
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define SRST_DDRCTRL1		167
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define SRST_DDRCTRL1_APB	168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define SRST_DDRPHY1_CTRL	169
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define SRST_DDRMSCH0		170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define SRST_DDRMSCH1		171
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define SRST_CRYPTO		174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define SRST_C2C_HOST		175
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define SRST_LCDC1_AXI		176
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define SRST_LCDC1_AHB		177
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define SRST_LCDC1_DCLK		178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define SRST_UART0		179
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define SRST_UART1		180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define SRST_UART2		181
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define SRST_UART3		182
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define SRST_UART4		183
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define SRST_SIMC		186
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define SRST_PS2C		187
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define SRST_TSP		188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define SRST_TSP_CLKIN0		189
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define SRST_TSP_CLKIN1		190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define SRST_TSP_27M		191
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #endif