^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Jeffy Chen <jeffy.chen@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /* core clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define PLL_APLL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define PLL_DPLL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define PLL_CPLL 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define PLL_GPLL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define ARMCLK 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* sclk gates (special clocks) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SCLK_SPI0 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SCLK_NANDC 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SCLK_SDMMC 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SCLK_SDIO 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SCLK_EMMC 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SCLK_TSADC 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SCLK_UART0 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SCLK_UART1 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SCLK_UART2 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SCLK_I2S0 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SCLK_I2S1 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SCLK_I2S2 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SCLK_SPDIF 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SCLK_TIMER0 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SCLK_TIMER1 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SCLK_TIMER2 87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SCLK_TIMER3 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SCLK_TIMER4 89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SCLK_TIMER5 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SCLK_I2S_OUT 113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SCLK_SDMMC_DRV 114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SCLK_SDIO_DRV 115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SCLK_EMMC_DRV 117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SCLK_SDMMC_SAMPLE 118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SCLK_SDIO_SAMPLE 119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SCLK_SDIO_SRC 120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SCLK_EMMC_SAMPLE 121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SCLK_VOP 122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SCLK_HDMI_HDCP 123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SCLK_MAC_SRC 124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SCLK_MAC_EXTCLK 125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SCLK_MAC 126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SCLK_MAC_REFOUT 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SCLK_MAC_REF 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SCLK_MAC_RX 129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SCLK_MAC_TX 130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SCLK_MAC_PHY 131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SCLK_MAC_OUT 132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SCLK_VDEC_CABAC 133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SCLK_VDEC_CORE 134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SCLK_RGA 135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SCLK_HDCP 136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SCLK_HDMI_CEC 137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SCLK_CRYPTO 138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SCLK_TSP 139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SCLK_HSADC 140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SCLK_WIFI 141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SCLK_OTGPHY0 142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SCLK_OTGPHY1 143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SCLK_HDMI_PHY 144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* dclk gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define DCLK_VOP 190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define DCLK_HDMI_PHY 191
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* aclk gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define ACLK_DMAC 194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define ACLK_CPU 195
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define ACLK_VPU_PRE 196
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define ACLK_RKVDEC_PRE 197
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define ACLK_RGA_PRE 198
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define ACLK_IEP_PRE 199
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define ACLK_HDCP_PRE 200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define ACLK_VOP_PRE 201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define ACLK_VPU 202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define ACLK_RKVDEC 203
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define ACLK_IEP 204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define ACLK_RGA 205
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define ACLK_HDCP 206
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define ACLK_PERI 210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define ACLK_VOP 211
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define ACLK_GMAC 212
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define ACLK_GPU 213
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* pclk gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define PCLK_GPIO0 320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define PCLK_GPIO1 321
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define PCLK_GPIO2 322
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define PCLK_GPIO3 323
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define PCLK_VIO_H2P 324
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define PCLK_HDCP 325
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define PCLK_EFUSE_1024 326
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define PCLK_EFUSE_256 327
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define PCLK_GRF 329
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define PCLK_I2C0 332
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define PCLK_I2C1 333
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define PCLK_I2C2 334
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define PCLK_I2C3 335
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define PCLK_SPI0 338
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define PCLK_UART0 341
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define PCLK_UART1 342
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define PCLK_UART2 343
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define PCLK_TSADC 344
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define PCLK_PWM 350
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define PCLK_TIMER 353
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define PCLK_CPU 354
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define PCLK_PERI 363
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define PCLK_HDMI_CTRL 364
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define PCLK_HDMI_PHY 365
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define PCLK_GMAC 367
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* hclk gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define HCLK_I2S0_8CH 442
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define HCLK_I2S1_8CH 443
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define HCLK_I2S2_2CH 444
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define HCLK_SPDIF_8CH 445
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define HCLK_VOP 452
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define HCLK_NANDC 453
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define HCLK_SDMMC 456
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define HCLK_SDIO 457
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define HCLK_EMMC 459
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define HCLK_CPU 460
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define HCLK_VPU_PRE 461
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define HCLK_RKVDEC_PRE 462
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define HCLK_VIO_PRE 463
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define HCLK_VPU 464
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define HCLK_RKVDEC 465
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define HCLK_VIO 466
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define HCLK_RGA 467
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define HCLK_IEP 468
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define HCLK_VIO_H2P 469
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define HCLK_HDCP_MMU 470
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define HCLK_HOST0 471
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define HCLK_HOST1 472
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define HCLK_HOST2 473
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define HCLK_OTG 474
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define HCLK_TSP 475
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define HCLK_M_CRYPTO 476
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define HCLK_S_CRYPTO 477
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define HCLK_PERI 478
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define CLK_NR_CLKS (HCLK_PERI + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* soft-reset indices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define SRST_CORE0_PO 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define SRST_CORE1_PO 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define SRST_CORE2_PO 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define SRST_CORE3_PO 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define SRST_CORE0 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define SRST_CORE1 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define SRST_CORE2 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define SRST_CORE3 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define SRST_CORE0_DBG 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define SRST_CORE1_DBG 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define SRST_CORE2_DBG 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define SRST_CORE3_DBG 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define SRST_TOPDBG 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define SRST_ACLK_CORE 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define SRST_NOC 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define SRST_L2C 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define SRST_CPUSYS_H 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define SRST_BUSSYS_H 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define SRST_SPDIF 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define SRST_INTMEM 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define SRST_ROM 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define SRST_OTG_ADP 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define SRST_I2S0 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define SRST_I2S1 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define SRST_I2S2 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define SRST_ACODEC_P 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define SRST_DFIMON 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define SRST_MSCH 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define SRST_EFUSE1024 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define SRST_EFUSE256 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define SRST_GPIO0 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define SRST_GPIO1 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define SRST_GPIO2 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define SRST_GPIO3 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define SRST_PERIPH_NOC_A 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define SRST_PERIPH_NOC_BUS_H 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define SRST_PERIPH_NOC_P 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define SRST_UART0 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define SRST_UART1 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define SRST_UART2 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define SRST_PHYNOC 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define SRST_I2C0 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define SRST_I2C1 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define SRST_I2C2 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define SRST_I2C3 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define SRST_PWM 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define SRST_A53_GIC 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define SRST_DAP 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define SRST_DAP_NOC 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define SRST_CRYPTO 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define SRST_SGRF 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define SRST_GRF 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define SRST_GMAC 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define SRST_PERIPH_NOC_H 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define SRST_MACPHY 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define SRST_DMA 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define SRST_NANDC 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define SRST_USBOTG 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define SRST_OTGC 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define SRST_USBHOST0 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define SRST_HOST_CTRL0 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define SRST_USBHOST1 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define SRST_HOST_CTRL1 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define SRST_USBHOST2 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define SRST_HOST_CTRL2 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define SRST_USBPOR0 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define SRST_USBPOR1 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define SRST_DDRMSCH 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define SRST_SMART_CARD 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define SRST_SDMMC 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define SRST_SDIO 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define SRST_EMMC 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define SRST_SPI 84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define SRST_TSP_H 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define SRST_TSP 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define SRST_TSADC 87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define SRST_DDRPHY 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define SRST_DDRPHY_P 89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define SRST_DDRCTRL 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define SRST_DDRCTRL_P 91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define SRST_HOST0_ECHI 92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define SRST_HOST1_ECHI 93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define SRST_HOST2_ECHI 94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define SRST_VOP_NOC_A 95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define SRST_HDMI_P 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define SRST_VIO_ARBI_H 97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define SRST_IEP_NOC_A 98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define SRST_VIO_NOC_H 99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define SRST_VOP_A 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define SRST_VOP_H 101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define SRST_VOP_D 102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define SRST_UTMI0 103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define SRST_UTMI1 104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define SRST_UTMI2 105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define SRST_UTMI3 106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define SRST_RGA 107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define SRST_RGA_NOC_A 108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define SRST_RGA_A 109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define SRST_RGA_H 110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define SRST_HDCP_A 111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define SRST_VPU_A 112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define SRST_VPU_H 113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define SRST_VPU_NOC_A 116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define SRST_VPU_NOC_H 117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define SRST_RKVDEC_A 118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define SRST_RKVDEC_NOC_A 119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define SRST_RKVDEC_H 120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define SRST_RKVDEC_NOC_H 121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define SRST_RKVDEC_CORE 122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define SRST_RKVDEC_CABAC 123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define SRST_IEP_A 124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define SRST_IEP_H 125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define SRST_GPU_A 126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define SRST_GPU_NOC_A 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define SRST_CORE_DBG 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define SRST_DBG_P 129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define SRST_TIMER0 130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define SRST_TIMER1 131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define SRST_TIMER2 132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define SRST_TIMER3 133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define SRST_TIMER4 134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define SRST_TIMER5 135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define SRST_VIO_H2P 136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define SRST_HDMIPHY 139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define SRST_VDAC 140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define SRST_TIMER_6CH_P 141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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