Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (c) 2014 MundoReader S.L.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * Author: Heiko Stuebner <heiko@sntech.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3188_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #define _DT_BINDINGS_CLK_ROCKCHIP_RK3188_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <dt-bindings/clock/rk3188-cru-common.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /* soft-reset indices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define SRST_PTM_CORE2		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define SRST_PTM_CORE3		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define SRST_CORE2		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define SRST_CORE3		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define SRST_CORE2_DBG		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SRST_CORE3_DBG		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SRST_TIMER2		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SRST_TIMER4		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SRST_I2S0		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SRST_TIMER5		25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SRST_TIMER3		29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SRST_TIMER6		31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SRST_PTM3		36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SRST_PTM3_ATB		37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SRST_GPS		67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SRST_HSICPHY		75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SRST_TIMER		78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SRST_PTM2		92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SRST_CORE2_WDT		94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SRST_CORE3_WDT		95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SRST_PTM2_ATB		111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SRST_HSIC		117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SRST_CTI2		118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SRST_CTI2_APB		119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SRST_GPU_BRIDGE		121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SRST_CTI3		123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SRST_CTI3_APB		124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #endif