^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2014 MundoReader S.L.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Heiko Stuebner <heiko@sntech.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3188_COMMON_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define _DT_BINDINGS_CLK_ROCKCHIP_RK3188_COMMON_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /* core clocks from */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define PLL_APLL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define PLL_DPLL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define PLL_CPLL 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define PLL_GPLL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define CORE_PERI 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define CORE_L2C 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define ARMCLK 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* sclk gates (special clocks) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SCLK_UART0 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SCLK_UART1 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SCLK_UART2 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SCLK_UART3 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SCLK_MAC 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SCLK_SPI0 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SCLK_SPI1 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SCLK_SARADC 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SCLK_SDMMC 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SCLK_SDIO 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SCLK_EMMC 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SCLK_I2S0 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SCLK_I2S1 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SCLK_I2S2 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SCLK_SPDIF 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SCLK_CIF0 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SCLK_CIF1 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SCLK_OTGPHY0 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SCLK_OTGPHY1 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SCLK_HSADC 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SCLK_TIMER0 84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SCLK_TIMER1 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SCLK_TIMER2 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SCLK_TIMER3 87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SCLK_TIMER4 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SCLK_TIMER5 89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SCLK_TIMER6 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SCLK_JTAG 91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SCLK_SMC 92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SCLK_TSADC 93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define DCLK_LCDC0 190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define DCLK_LCDC1 191
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* aclk gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define ACLK_DMA1 192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define ACLK_DMA2 193
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define ACLK_GPS 194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define ACLK_LCDC0 195
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define ACLK_LCDC1 196
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define ACLK_GPU 197
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define ACLK_SMC 198
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define ACLK_CIF1 199
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define ACLK_IPP 200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define ACLK_RGA 201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define ACLK_CIF0 202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define ACLK_CPU 203
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define ACLK_PERI 204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define ACLK_VEPU 205
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define ACLK_VDPU 206
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define ACLK_CPU_PRE 207
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* pclk gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define PCLK_GRF 320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define PCLK_PMU 321
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define PCLK_TIMER0 322
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define PCLK_TIMER1 323
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define PCLK_TIMER2 324
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define PCLK_TIMER3 325
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define PCLK_PWM01 326
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define PCLK_PWM23 327
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define PCLK_SPI0 328
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define PCLK_SPI1 329
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define PCLK_SARADC 330
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define PCLK_WDT 331
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define PCLK_UART0 332
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define PCLK_UART1 333
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define PCLK_UART2 334
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define PCLK_UART3 335
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define PCLK_I2C0 336
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define PCLK_I2C1 337
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define PCLK_I2C2 338
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define PCLK_I2C3 339
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define PCLK_I2C4 340
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define PCLK_GPIO0 341
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define PCLK_GPIO1 342
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define PCLK_GPIO2 343
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define PCLK_GPIO3 344
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define PCLK_GPIO4 345
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define PCLK_GPIO6 346
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define PCLK_EFUSE 347
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define PCLK_TZPC 348
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define PCLK_TSADC 349
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define PCLK_CPU 350
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define PCLK_PERI 351
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define PCLK_DDRUPCTL 352
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define PCLK_PUBL 353
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* hclk gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define HCLK_SDMMC 448
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define HCLK_SDIO 449
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define HCLK_EMMC 450
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define HCLK_OTG0 451
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define HCLK_EMAC 452
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define HCLK_SPDIF 453
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define HCLK_I2S0_2CH 454
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define HCLK_I2S1_2CH 455
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define HCLK_I2S_8CH 456
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define HCLK_OTG1 457
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define HCLK_HSIC 458
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define HCLK_HSADC 459
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define HCLK_PIDF 460
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define HCLK_LCDC0 461
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define HCLK_LCDC1 462
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define HCLK_ROM 463
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define HCLK_CIF0 464
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define HCLK_IPP 465
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define HCLK_RGA 466
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define HCLK_NANDC0 467
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define HCLK_CPU 468
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define HCLK_PERI 469
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define HCLK_CIF1 470
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define HCLK_VEPU 471
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define HCLK_VDPU 472
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define HCLK_HDMI 473
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define CLK_NR_CLKS (HCLK_HDMI + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* soft-reset indices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define SRST_MCORE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define SRST_CORE0 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define SRST_CORE1 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define SRST_MCORE_DBG 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define SRST_CORE0_DBG 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define SRST_CORE1_DBG 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define SRST_CORE0_WDT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define SRST_CORE1_WDT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define SRST_STRC_SYS 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define SRST_L2C 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define SRST_CPU_AHB 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define SRST_AHB2APB 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define SRST_DMA1 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define SRST_INTMEM 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define SRST_ROM 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define SRST_SPDIF 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define SRST_TIMER0 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define SRST_TIMER1 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define SRST_EFUSE 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define SRST_GPIO0 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define SRST_GPIO1 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define SRST_GPIO2 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define SRST_GPIO3 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define SRST_UART0 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define SRST_UART1 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define SRST_UART2 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define SRST_UART3 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define SRST_I2C0 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define SRST_I2C1 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define SRST_I2C2 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define SRST_I2C3 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define SRST_I2C4 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define SRST_PWM0 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define SRST_PWM1 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define SRST_DAP_PO 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define SRST_DAP 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define SRST_DAP_SYS 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define SRST_TPIU_ATB 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define SRST_PMU_APB 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define SRST_GRF 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define SRST_PMU 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define SRST_PERI_AXI 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define SRST_PERI_AHB 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define SRST_PERI_APB 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define SRST_PERI_NIU 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define SRST_CPU_PERI 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define SRST_EMEM_PERI 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define SRST_USB_PERI 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define SRST_DMA2 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define SRST_SMC 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define SRST_MAC 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define SRST_NANC0 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define SRST_USBOTG0 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define SRST_USBPHY0 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define SRST_OTGC0 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define SRST_USBOTG1 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define SRST_USBPHY1 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define SRST_OTGC1 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define SRST_HSADC 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define SRST_PIDFILTER 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define SRST_DDR_MSCH 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define SRST_TZPC 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define SRST_SDMMC 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define SRST_SDIO 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define SRST_EMMC 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define SRST_SPI0 84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define SRST_SPI1 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define SRST_WDT 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define SRST_SARADC 87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define SRST_DDRPHY 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define SRST_DDRPHY_APB 89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define SRST_DDRCTL 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define SRST_DDRCTL_APB 91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define SRST_DDRPUB 93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define SRST_VIO0_AXI 98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define SRST_VIO0_AHB 99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define SRST_LCDC0_AXI 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define SRST_LCDC0_AHB 101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define SRST_LCDC0_DCLK 102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define SRST_LCDC1_AXI 103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define SRST_LCDC1_AHB 104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define SRST_LCDC1_DCLK 105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define SRST_IPP_AXI 106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define SRST_IPP_AHB 107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define SRST_RGA_AXI 108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define SRST_RGA_AHB 109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define SRST_CIF0 110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define SRST_VCODEC_AXI 112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define SRST_VCODEC_AHB 113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define SRST_VIO1_AXI 114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define SRST_VCODEC_CPU 115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define SRST_VCODEC_NIU 116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define SRST_GPU 120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define SRST_GPU_NIU 122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define SRST_TFUN_ATB 125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define SRST_TFUN_APB 126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define SRST_CTI4_APB 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define SRST_TPIU_APB 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define SRST_TRACE 129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define SRST_CORE_DBG 130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define SRST_DBG_APB 131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define SRST_CTI0 132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define SRST_CTI0_APB 133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define SRST_CTI1 134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define SRST_CTI1_APB 135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define SRST_PTM_CORE0 136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define SRST_PTM_CORE1 137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define SRST_PTM0 138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define SRST_PTM0_ATB 139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define SRST_PTM1 140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define SRST_PTM1_ATB 141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define SRST_CTM 142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define SRST_TS 143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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