^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2014 MundoReader S.L.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Heiko Stuebner <heiko@sntech.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3066A_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define _DT_BINDINGS_CLK_ROCKCHIP_RK3066A_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <dt-bindings/clock/rk3188-cru-common.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /* soft-reset indices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define SRST_SRST1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define SRST_SRST2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define SRST_L2MEM 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define SRST_I2S0 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SRST_I2S1 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SRST_I2S2 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SRST_TIMER2 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SRST_GPIO4 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SRST_GPIO6 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SRST_TSADC 92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SRST_HDMI 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SRST_HDMI_APB 97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SRST_CIF1 111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #endif