^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Xing Zheng <zhengxing@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /* core clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define PLL_APLL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define PLL_DPLL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define PLL_GPLL 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define ARMCLK 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* sclk gates (special clocks) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define SCLK_GPU 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SCLK_SPI 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SCLK_SDMMC 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SCLK_SDIO 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SCLK_EMMC 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SCLK_NANDC 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SCLK_UART0 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SCLK_UART1 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SCLK_UART2 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SCLK_I2S 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SCLK_SPDIF 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SCLK_TIMER0 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SCLK_TIMER1 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SCLK_TIMER2 87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SCLK_TIMER3 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SCLK_OTGPHY0 93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SCLK_LCDC 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SCLK_HDMI 109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SCLK_HEVC 111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SCLK_I2S_OUT 113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SCLK_SDMMC_DRV 114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SCLK_SDIO_DRV 115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SCLK_EMMC_DRV 117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SCLK_SDMMC_SAMPLE 118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SCLK_SDIO_SAMPLE 119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SCLK_EMMC_SAMPLE 121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SCLK_PVTM_CORE 123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SCLK_PVTM_GPU 124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SCLK_PVTM_VIDEO 125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SCLK_I2S_FRAC 126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SCLK_I2S_PRE 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SCLK_MAC 151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SCLK_MACREF 152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SCLK_MACPLL 153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SCLK_SFC 160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* aclk gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define ACLK_DMAC2 194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define ACLK_LCDC 197
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define ACLK_VIO 203
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define ACLK_VCODEC 208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define ACLK_CPU 209
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define ACLK_PERI 210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define ACLK_HEVC 211
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* pclk gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define PCLK_GPIO0 320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define PCLK_GPIO1 321
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define PCLK_GPIO2 322
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define PCLK_GRF 329
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define PCLK_I2C0 332
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PCLK_I2C1 333
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define PCLK_I2C2 334
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define PCLK_SPI 338
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define PCLK_UART0 341
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define PCLK_UART1 342
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define PCLK_UART2 343
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define PCLK_PWM 350
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define PCLK_TIMER 353
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define PCLK_HDMI 360
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define PCLK_CPU 362
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define PCLK_PERI 363
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define PCLK_DDRUPCTL 364
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define PCLK_WDT 368
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define PCLK_ACODEC 369
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* hclk gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define HCLK_OTG0 449
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define HCLK_OTG1 450
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define HCLK_NANDC 453
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define HCLK_SFC 454
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define HCLK_SDMMC 456
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define HCLK_SDIO 457
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define HCLK_EMMC 459
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define HCLK_MAC 460
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define HCLK_I2S 462
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define HCLK_LCDC 465
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define HCLK_ROM 467
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define HCLK_VIO_BUS 472
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define HCLK_VCODEC 476
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define HCLK_CPU 477
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define HCLK_PERI 478
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define CLK_NR_CLKS (HCLK_PERI + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* soft-reset indices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SRST_CORE0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SRST_CORE1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SRST_CORE0_DBG 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SRST_CORE1_DBG 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SRST_CORE0_POR 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define SRST_CORE1_POR 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SRST_L2C 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define SRST_TOPDBG 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define SRST_STRC_SYS_A 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define SRST_PD_CORE_NIU 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SRST_TIMER2 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define SRST_CPUSYS_H 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define SRST_AHB2APB_H 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define SRST_TIMER3 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define SRST_INTMEM 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define SRST_ROM 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define SRST_PERI_NIU 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define SRST_I2S 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define SRST_DDR_PLL 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define SRST_GPU_DLL 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define SRST_TIMER0 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define SRST_TIMER1 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define SRST_CORE_DLL 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define SRST_EFUSE_P 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define SRST_ACODEC_P 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define SRST_GPIO0 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define SRST_GPIO1 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define SRST_GPIO2 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define SRST_UART0 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define SRST_UART1 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define SRST_UART2 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define SRST_I2C0 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define SRST_I2C1 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define SRST_I2C2 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define SRST_SFC 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define SRST_PWM0 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define SRST_DAP 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define SRST_DAP_SYS 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define SRST_GRF 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define SRST_PERIPHSYS_A 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define SRST_PERIPHSYS_H 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define SRST_PERIPHSYS_P 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define SRST_CPU_PERI 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define SRST_EMEM_PERI 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define SRST_USB_PERI 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define SRST_DMA2 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define SRST_MAC 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define SRST_NANDC 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define SRST_USBOTG0 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define SRST_OTGC0 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define SRST_USBOTG1 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define SRST_OTGC1 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define SRST_DDRMSCH 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define SRST_MMC0 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define SRST_SDIO 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define SRST_EMMC 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define SRST_SPI0 84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define SRST_WDT 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define SRST_DDRPHY 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define SRST_DDRPHY_P 89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define SRST_DDRCTRL 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define SRST_DDRCTRL_P 91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define SRST_HDMI_P 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define SRST_VIO_BUS_H 99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define SRST_UTMI0 103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define SRST_UTMI1 104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define SRST_USBPOR 105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define SRST_VCODEC_A 112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define SRST_VCODEC_H 113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define SRST_VIO1_A 114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define SRST_HEVC 115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define SRST_VCODEC_NIU_A 116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define SRST_LCDC1_A 117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define SRST_LCDC1_H 118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define SRST_LCDC1_D 119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define SRST_GPU 120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define SRST_GPU_NIU_A 122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define SRST_DBG_P 131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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