Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK1808_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) #define _DT_BINDINGS_CLK_ROCKCHIP_RK1808_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) /* core clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #define PLL_APLL		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #define PLL_DPLL		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #define PLL_CPLL		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #define PLL_GPLL		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define PLL_NPLL		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define PLL_PPLL		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define ARMCLK			7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define DCLK_VOPRAW		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define DCLK_VOPLITE		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define DCLK_CIF		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define XIN24M_DIV		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) /* sclk (special clocks) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define USB480M			20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define SCLK_PVTM_CORE		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define SCLK_NPU		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define SCLK_PVTM_NPU		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define SCLK_DDRCLK		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define SCLK_I2S0_8CH_TX_MUX	25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define SCLK_I2S0_8CH_RX_MUX	26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define SCLK_RTC32K_PMU		27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define SCLK_TXESC		28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define SCLK_RGA		29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define SCLK_ISP		30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define SCLK_CIF_OUT		31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define SCLK_PCIE_AUX		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define SCLK_USB3_OTG0_REF	33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define SCLK_USB3_OTG0_SUSPEND	34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define SCLK_SDIO_DIV		35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define SCLK_SDIO_DIV50		36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define SCLK_SDIO		37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define SCLK_SDIO_DRV		38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define SCLK_SDIO_SAMPLE	39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define SCLK_EMMC_DIV		40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define SCLK_EMMC_DIV50		41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define SCLK_EMMC		42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define SCLK_EMMC_DRV		43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define SCLK_EMMC_SAMPLE	44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define SCLK_SDMMC_DIV		45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define SCLK_SDMMC_DIV50	46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define SCLK_SDMMC		47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define SCLK_SDMMC_DRV		48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define SCLK_SDMMC_SAMPLE	49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define SCLK_SFC		50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define SCLK_GMAC_OUT		51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define SCLK_GMAC_SRC		52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define SCLK_GMAC		53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define SCLK_GMAC_REF		54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define SCLK_GMAC_REFOUT	55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define SCLK_GMAC_RGMII_SPEED	56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define SCLK_GMAC_RMII_SPEED	57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define SCLK_GMAC_RX_TX		58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define SCLK_CRYPTO		59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define SCLK_CRYPTO_APK		60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define SCLK_UART1		61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define SCLK_UART2		62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define SCLK_UART3		63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define SCLK_UART4		64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define SCLK_UART5		65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define SCLK_UART6		66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define SCLK_UART7		67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define SCLK_I2C1		68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define SCLK_I2C2		69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define SCLK_I2C3		70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define SCLK_I2C4		71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define SCLK_I2C5		72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define SCLK_SPI0		73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define SCLK_SPI1		74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define SCLK_SPI2		75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define SCLK_TSADC		76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define SCLK_SARADC		77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define SCLK_EFUSE_S		78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define SCLK_EFUSE_NS		79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define DBCLK_GPIO1		80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define DBCLK_GPIO2		81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define DBCLK_GPIO3		82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define DBCLK_GPIO4		83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define SCLK_PWM0		84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define SCLK_PWM1		85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define SCLK_PWM2		86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define SCLK_TIMER0		87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define SCLK_TIMER1		88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define SCLK_TIMER2		89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define SCLK_TIMER3		90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define SCLK_TIMER4		91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define SCLK_TIMER5		92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define SCLK_PDM		93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define SCLK_I2S0_8CH_TX_SRC	94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define SCLK_I2S0_8CH_TX	95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define SCLK_I2S0_8CH_TX_OUT	96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define SCLK_I2S0_8CH_RX_SRC	97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define SCLK_I2S0_8CH_RX	98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SCLK_I2S0_8CH_RX_OUT	99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SCLK_I2S1_2CH_SRC	100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define SCLK_I2S1_2CH		101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SCLK_I2S1_2CH_OUT	102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SCLK_WIFI_PMU		103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SCLK_UART0_PMU		104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SCLK_PVTM_PMU		105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SCLK_PMU_I2C0		106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define DBCLK_PMU_GPIO0		107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SCLK_REF24M_PMU		108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define SCLK_USBPHY_REF		109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define SCLK_MIPIDSIPHY_REF	110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define SCLK_PCIEPHY_REF	111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define SCLK_RTC32K_FRAC	112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SCLK_32K_IOE		113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* aclk gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define ACLK_GIC_PRE		145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define ACLK_GIC		146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define ACLK_VPU		147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define ACLK_NPU		148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define ACLK_IMEM_PRE		153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define ACLK_IMEM0		154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define ACLK_IMEM1		155
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define ACLK_IMEM2		156
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define ACLK_IMEM3		157
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define HSCLK_VIO		158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define ACLK_VOPRAW		159
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define ACLK_VOPLITE		160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define ACLK_RGA		161
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define ACLK_ISP		162
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define ACLK_CIF		163
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define HSCLK_PCIE		164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define ACLK_USB3OTG		165
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define ACLK_PCIE		166
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define ACLK_PCIE_MST		167
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define ACLK_PCIE_SLV		168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define MSCLK_PERI		169
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define ACLK_GMAC		170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define HSCLK_BUS_PRE		171
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define ACLK_CRYPTO		172
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define ACLK_DCF		173
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define ACLK_DMAC		174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* hclk gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define HCLK_NPU		199
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define HCLK_VPU		200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define LSCLK_VIO		201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define HCLK_VOPRAW		202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define HCLK_VOPLITE		203
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define HCLK_RGA		204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define HCLK_ISP		205
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define LSCLK_PCIE		206
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define HCLK_HOST		207
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define LSCLK_PERI		208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define HCLK_SDIO		209
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define HCLK_EMMC		210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define HCLK_SDMMC		211
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define HCLK_SFC		212
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define MSCLK_BUS_PRE		213
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define HCLK_ROM		214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define HCLK_CRYPTO		215
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define HCLK_VAD		216
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define HCLK_PDM		217
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define HCLK_I2S0_8CH		218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define HCLK_I2S1_2CH		219
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define MSCLK_CORE_NIU		220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define HSCLK_IMEM		221
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define HCLK_HOST_ARB		222
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define HCLK_CIF		223
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* pclk gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define PCLK_DDR		250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define PCLK_DSI_TX		251
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define PCLK_CSI_TX		252
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define PCLK_CSI2HOST		253
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define PCLK_PCIE		254
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define PCLK_GMAC		255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define LSCLK_BUS_PRE		256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define PCLK_DCF		257
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define PCLK_UART1		258
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define PCLK_UART2		259
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define PCLK_UART3		260
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define PCLK_UART4		261
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define PCLK_UART5		262
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define PCLK_UART6		263
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define PCLK_UART7		264
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define PCLK_I2C1		265
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define PCLK_I2C2		266
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define PCLK_I2C3		267
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define PCLK_I2C4		268
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define PCLK_I2C5		269
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define PCLK_SPI0		270
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define PCLK_SPI1		271
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define PCLK_SPI2		272
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define PCLK_TSADC		273
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define PCLK_SARADC		274
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define PCLK_EFUSE		275
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define PCLK_GPIO1		276
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define PCLK_GPIO2		277
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define PCLK_GPIO3		278
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define PCLK_GPIO4		279
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define PCLK_PWM0		280
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define PCLK_PWM1		281
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define PCLK_PWM2		282
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define PCLK_TIMER		283
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define PCLK_WDT		284
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define PCLK_MIPIDSIPHY		285
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define PCLK_MIPICSIPHY		286
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define PCLK_DDRMON		287
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define PCLK_DDRC		289
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define PCLK_MSCH		290
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define PCLK_STDBY		291
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define PCLK_GPIO0_PMU		292
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define PCLK_UART0_PMU		293
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define PCLK_I2C0_PMU		294
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define PCLK_USB3PHY_PIPE	295
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define PCLK_PMU_PRE		296
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define CLK_NR_CLKS		(PCLK_PMU_PRE + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* soft-reset indices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* cru_softrst_con0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define SRST_CORE0_PO		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define SRST_CORE1_PO		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define SRST_CORE0		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define SRST_CORE1		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define SRST_CORE0_DBG		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define SRST_CORE1_DBG		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define SRST_TOPDBG		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define SRST_CORE_NOC		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define SRST_STRC_A		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define SRST_L2C		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define SRST_DAP                10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define SRST_CORE_MSNIU		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define SRST_GIC2CORE		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define SRST_CORE2GIC		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define SRST_CORE_PRF_A		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define SRST_CORE_GRF_P		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* cru_softrst_con1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define SRST_DDRPHY		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define SRST_DDRPHY_P		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define SRST_UPCTL2		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define SRST_UPCTL2_A		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define SRST_UPCTL2_P		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define SRST_MSCH		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define SRST_MSCH_P		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define SRST_DDRMON_P		25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define SRST_DDRSTDBY_P		26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define SRST_DDRSTDBY		27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define SRST_DDRGRF_P		28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define SRST_AXI_SPLIT_A	29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define SRST_DDRDFI_CTL		30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define SRST_DDRDFI_CTL_P	31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* cru_softrst_con2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define SRST_GIC500_NIU_A	32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define SRST_GIC500_A		33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define SRST_GIC_CORE2GIC	34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define SRST_GIC_GIC2CORE	35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define SRST_NPU_CORE		36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define SRST_NPU_A		37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define SRST_NPU_H		38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define SRST_NPU_NIU_A		39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define SRST_NPU_NIU_H		40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define SRST_NPU2MEM_A		41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define SRST_NPU_PVTM		42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define SRST_CORE_PVTM		43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define SRST_GIC_SPINLOCK_A	47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* cru_softrst_con3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define SRST_PCIE_NIU_H		48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define SRST_PCIE_NIU_L		49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define SRST_PCIEGRF_P		50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define SRST_PCIECTL_P		51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define SRST_PCIECTL_POWERUP	52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define SRST_PCIECTL_MST_A	53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define SRST_PCIECTL_SLV_A	54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define SRST_PCIECTL_DBI_A	55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define SRST_PCIECTL_BUTTON	56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define SRST_PCIECTL_PE		57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define SRST_PCIECTL_CORE	58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define SRST_PCIECTL_NSTICKY	59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define SRST_PCIECTL_STICKY	60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define SRST_PCIECTL_PWR	61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define SRST_PCIE_NIU_A		62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define SRST_PCIE_NIU_P		63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /* cru_softrst_con4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define SRST_PCIEPHY_POR	64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define SRST_PCIEPHY_P		65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define SRST_PCIEPHY_PIPE	66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define SRST_USBPHY_POR		67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define SRST_USBPHY_OTG_PORT	68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define SRST_USBPHY_HOST_PORT	69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define SRST_USB3PHY_GRF_P	70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define SRST_USB2PHY_GRF_P	71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define SRST_USB3_OTG_A		72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define SRST_USB2HOST_H		73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define SRST_USB2HOST_ARB_H	74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define SRSTUSB2HOST_UTMI	75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* cru_softrst_con5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define SRST_IMEM0_A		80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define SRST_IMEM1_A		81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define SRST_IMEM2_A		82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define SRST_IMEM3_A		83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define SRST_IMEM0_NIU_A	84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define SRST_IMEM1_NIU_A	85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define SRST_IMEM2_NIU_A	86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define SRST_IMEM3_NIU_A	87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define SRST_IMEM_NIU_H		88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define SRST_VPU_NIU_A		92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define SRST_VPU_NIU_H		93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define SRST_VPU_A		94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define SRST_VPU_H		95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /* cru_softrst_con6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define SRST_VIO_NIU_H		96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define SRST_VIO_NIU_L		97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define SRST_VOPRAW_A		98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define SRST_VOPRAW_H		99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define SRST_VOPRAW_D		100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define SRST_VOPLITE_A		101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define SRST_VOPLITE_H		102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define SRST_VOPLITE_D		103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define SRST_MIPIDSI_HOST_P	104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define SRST_CSITX_P		105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define SRST_CSITX_TXBYTEHS	106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define SRST_CSITX_TXESC	107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define SRST_CSITX_CAM		108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define SRST_CSITX_I		109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* cru_softrst_con7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define SRST_RGA_A		112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define SRST_RGA_H		113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define SRST_RGA		114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define SRST_CSI2HOST_P		115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define SRST_CIF_A		116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define SRST_CIF_H		117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define SRST_CIF_I		118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define SRST_CIF_PCLKIN		119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define SRST_CIF_D		120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define SRST_ISP_H		121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define SRST_ISP		122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define SRST_MIPICSIPHY_P	124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define SRST_MIPIDSIPHY_P	125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /* cru_softrst_con8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define SRST_PERI_NIU_H		128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define SRST_PERI_NIU_L		129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define SRST_PDMMC_NIU_H	132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define SRST_SDMMC_H		133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define SRST_SDIO_H		134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define SRST_EMMC_H		135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define SRST_SFC_H		136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define SRST_SFC		137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define SRST_GMAC_NIU_A		140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define SRST_GMAC_NIU_H		141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define SRST_GMAC_NIU_P		142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define SRST_GAMC_A		143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) /* cru_softrst_con9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define SRST_PMU_NIU_P		144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define SRST_PMU_SGRF_P		145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define SRST_PMU_GRF_P		146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define SRST_PMU_PMU		147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define SRST_PMU_MEM_P		148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define SRST_PMU_GPIO0_P	149
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define SRST_PMU_UART0_P	150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define SRST_PMU_CRU		151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define SRST_PMU_PVTM		152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define SRST_PMU_UART0		153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define SRST_PMU_NIU_H		154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define SRST_PMU_DDR_FAIL_SAVE	155
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define SRST_PMU_I2C0_P		156
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define SRST_PMU_I2C0		157
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define SRST_PMU_GPIO0_DB	158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /* cru_softrst_con10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define SRST_AUDIO_NIU_H	160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define SRST_VAD_H		161
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define SRST_PDM_H		162
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define SRST_PDM		163
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define SRST_I2S0_H		164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define SRST_I2S0_TX		165
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define SRST_I2S1_H		166
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define SRST_I2S1		167
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define SRST_I2S0_RX		168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) /* cru_softrst_con11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define SRST_BUS_NIU_M		176
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define SRST_BUS_NIU_L		177
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define SRST_TOP_NIU_P		178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define SRST_ROM_H		179
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define SRST_CRYPTO_A		180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define SRST_CRYPTO_H		181
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define SRST_CRYPTO_CORE	182
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define SRST_CRYPTO_APK		183
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define SRST_DCF_A		184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define SRST_DCF_P		185
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define SRST_UART1_P		186
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define SRST_UART1		187
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define SRST_UART2_P		188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define SRST_UART2		189
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define SRST_UART3_P		190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define SRST_UART3		191
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /* cru_softrst_con12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define SRST_UART4_P		192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define SRST_UART4		193
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define SRST_UART5_P		194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define SRST_UART5		195
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define SRST_UART6_P		196
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define SRST_UART6		197
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define SRST_UART7_P		198
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define SRST_UART7		199
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define SRST_I2C1_P		200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define SRST_I2C1		201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define SRST_I2C2_P		202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define SRST_I2C2		203
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define SRST_I2C3_P		204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define SRST_I2C3		205
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define SRST_PWM0_P		206
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define SRST_PWM0		207
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) /* cru_softrst_con13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define SRST_PWM1_P		208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define SRST_PWM1		209
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define SRST_PWM2_P		210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define SRST_PWM2		211
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define SRST_SPI0_P		212
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define SRST_SPI0		213
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define SRST_SPI1_P		214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define SRST_SPI1		215
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define SRST_SPI2_P		216
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define SRST_SPI2		217
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define SRST_BUS_SGRF_P		218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define SRST_BUS_GRF_P		219
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define SRST_TIMER_P		220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define SRST_TIMER0		221
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define SRST_TIMER1		222
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define SRST_TIMER2		223
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /* cru_softrst_con14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define SRST_TIMER3		224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define SRST_TIMER4		225
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define SRST_TIMER5		226
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define SRST_WDT_NS_P		227
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define SRST_EFUSE_NS_P		228
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define SRST_EFUSE_NS		229
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define SRST_GPIO1_P		230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define SRST_GPIO1_DB		231
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define SRST_GPIO2_P		232
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define SRST_GPIO2_DB		233
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define SRST_GPIO3_P		234
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define SRST_GPIO3_DB		235
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define SRST_GPIO4_P		236
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define SRST_GPIO4_DB		237
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define SRST_BUS_SUB_NIU_M	238
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /* cru_softrst_con15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define SRST_I2C4_P		240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define SRST_I2C4		241
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define SRST_I2C5_P		242
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define SRST_I2C5		243
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define SRST_SARADC		252
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define SRST_SARADC_P		253
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define SRST_TSADC_P		254
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define SRST_TSADC		255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #endif