^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2015 Renesas Electronics Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #ifndef __DT_BINDINGS_CLOCK_RENESAS_CPG_MSSR_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #define __DT_BINDINGS_CLOCK_RENESAS_CPG_MSSR_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define CPG_CORE 0 /* Core Clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define CPG_MOD 1 /* Module Clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #endif /* __DT_BINDINGS_CLOCK_RENESAS_CPG_MSSR_H__ */