^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * R9A06G032 sysctrl IDs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2018 Renesas Electronics Europe Limited
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Michel Pollet <michel.pollet@bp.renesas.com>, <buserror@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef __DT_BINDINGS_R9A06G032_SYSCTRL_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define __DT_BINDINGS_R9A06G032_SYSCTRL_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define R9A06G032_CLK_PLL_USB 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define R9A06G032_CLK_48 1 /* AKA CLK_PLL_USB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define R9A06G032_MSEBIS_CLK 3 /* AKA CLKOUT_D16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define R9A06G032_MSEBIM_CLK 3 /* AKA CLKOUT_D16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define R9A06G032_CLK_DDRPHY_PLLCLK 5 /* AKA CLKOUT_D1OR2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define R9A06G032_CLK50 6 /* AKA CLKOUT_D20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define R9A06G032_CLK25 7 /* AKA CLKOUT_D40 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define R9A06G032_CLK125 9 /* AKA CLKOUT_D8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define R9A06G032_CLK_P5_PG1 17 /* AKA DIV_P5_PG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define R9A06G032_CLK_REF_SYNC 21 /* AKA DIV_REF_SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define R9A06G032_CLK_25_PG4 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define R9A06G032_CLK_25_PG5 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define R9A06G032_CLK_25_PG6 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define R9A06G032_CLK_25_PG7 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define R9A06G032_CLK_25_PG8 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define R9A06G032_CLK_ADC 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define R9A06G032_CLK_ECAT100 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define R9A06G032_CLK_HSR100 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define R9A06G032_CLK_I2C0 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define R9A06G032_CLK_I2C1 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define R9A06G032_CLK_MII_REF 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define R9A06G032_CLK_NAND 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define R9A06G032_CLK_NOUSBP2_PG6 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define R9A06G032_CLK_P1_PG2 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define R9A06G032_CLK_P1_PG3 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define R9A06G032_CLK_P1_PG4 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define R9A06G032_CLK_P4_PG3 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define R9A06G032_CLK_P4_PG4 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define R9A06G032_CLK_P6_PG1 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define R9A06G032_CLK_P6_PG2 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define R9A06G032_CLK_P6_PG3 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define R9A06G032_CLK_P6_PG4 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define R9A06G032_CLK_PCI_USB 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define R9A06G032_CLK_QSPI0 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define R9A06G032_CLK_QSPI1 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define R9A06G032_CLK_RGMII_REF 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define R9A06G032_CLK_RMII_REF 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define R9A06G032_CLK_SDIO0 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define R9A06G032_CLK_SDIO1 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define R9A06G032_CLK_SERCOS100 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define R9A06G032_CLK_SLCD 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define R9A06G032_CLK_SPI0 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define R9A06G032_CLK_SPI1 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define R9A06G032_CLK_SPI2 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define R9A06G032_CLK_SPI3 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define R9A06G032_CLK_SPI4 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define R9A06G032_CLK_SPI5 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define R9A06G032_CLK_SWITCH 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define R9A06G032_HCLK_ECAT125 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define R9A06G032_HCLK_PINCONFIG 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define R9A06G032_HCLK_SERCOS 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define R9A06G032_HCLK_SGPIO2 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define R9A06G032_HCLK_SGPIO3 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define R9A06G032_HCLK_SGPIO4 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define R9A06G032_HCLK_TIMER0 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define R9A06G032_HCLK_TIMER1 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define R9A06G032_HCLK_USBF 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define R9A06G032_HCLK_USBH 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define R9A06G032_HCLK_USBPM 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define R9A06G032_CLK_48_PG_F 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define R9A06G032_CLK_48_PG4 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define R9A06G032_CLK_DDRPHY_PCLK 81 /* AKA CLK_REF_SYNC_D4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define R9A06G032_CLK_FW 81 /* AKA CLK_REF_SYNC_D4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define R9A06G032_CLK_CRYPTO 81 /* AKA CLK_REF_SYNC_D4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define R9A06G032_CLK_A7MP 84 /* AKA DIV_CA7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define R9A06G032_HCLK_CAN0 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define R9A06G032_HCLK_CAN1 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define R9A06G032_HCLK_DELTASIGMA 87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define R9A06G032_HCLK_PWMPTO 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define R9A06G032_HCLK_RSV 89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define R9A06G032_HCLK_SGPIO0 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define R9A06G032_HCLK_SGPIO1 91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define R9A06G032_RTOS_MDC 92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define R9A06G032_CLK_CM3 93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define R9A06G032_CLK_DDRC 94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define R9A06G032_CLK_ECAT25 95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define R9A06G032_CLK_HSR50 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define R9A06G032_CLK_HW_RTOS 97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define R9A06G032_CLK_SERCOS50 98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define R9A06G032_HCLK_ADC 99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define R9A06G032_HCLK_CM3 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define R9A06G032_HCLK_CRYPTO_EIP150 101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define R9A06G032_HCLK_CRYPTO_EIP93 102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define R9A06G032_HCLK_DDRC 103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define R9A06G032_HCLK_DMA0 104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define R9A06G032_HCLK_DMA1 105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define R9A06G032_HCLK_GMAC0 106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define R9A06G032_HCLK_GMAC1 107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define R9A06G032_HCLK_GPIO0 108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define R9A06G032_HCLK_GPIO1 109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define R9A06G032_HCLK_GPIO2 110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define R9A06G032_HCLK_HSR 111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define R9A06G032_HCLK_I2C0 112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define R9A06G032_HCLK_I2C1 113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define R9A06G032_HCLK_LCD 114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define R9A06G032_HCLK_MSEBI_M 115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define R9A06G032_HCLK_MSEBI_S 116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define R9A06G032_HCLK_NAND 117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define R9A06G032_HCLK_PG_I 118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define R9A06G032_HCLK_PG19 119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define R9A06G032_HCLK_PG20 120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define R9A06G032_HCLK_PG3 121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define R9A06G032_HCLK_PG4 122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define R9A06G032_HCLK_QSPI0 123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define R9A06G032_HCLK_QSPI1 124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define R9A06G032_HCLK_ROM 125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define R9A06G032_HCLK_RTC 126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define R9A06G032_HCLK_SDIO0 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define R9A06G032_HCLK_SDIO1 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define R9A06G032_HCLK_SEMAP 129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define R9A06G032_HCLK_SPI0 130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define R9A06G032_HCLK_SPI1 131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define R9A06G032_HCLK_SPI2 132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define R9A06G032_HCLK_SPI3 133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define R9A06G032_HCLK_SPI4 134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define R9A06G032_HCLK_SPI5 135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define R9A06G032_HCLK_SWITCH 136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define R9A06G032_HCLK_SWITCH_RG 137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define R9A06G032_HCLK_UART0 138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define R9A06G032_HCLK_UART1 139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define R9A06G032_HCLK_UART2 140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define R9A06G032_HCLK_UART3 141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define R9A06G032_HCLK_UART4 142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define R9A06G032_HCLK_UART5 143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define R9A06G032_HCLK_UART6 144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define R9A06G032_HCLK_UART7 145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define R9A06G032_CLK_UART0 146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define R9A06G032_CLK_UART1 147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define R9A06G032_CLK_UART2 148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define R9A06G032_CLK_UART3 149
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define R9A06G032_CLK_UART4 150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define R9A06G032_CLK_UART5 151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define R9A06G032_CLK_UART6 152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define R9A06G032_CLK_UART7 153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #endif /* __DT_BINDINGS_R9A06G032_SYSCTRL_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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