Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (C) 2016 Renesas Electronics Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * Copyright (C) 2017 Cogent Embedded, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #ifndef __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <dt-bindings/clock/renesas-cpg-mssr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /* r8a77970 CPG Core Clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define R8A77970_CLK_Z2			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define R8A77970_CLK_ZR			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define R8A77970_CLK_ZTR		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define R8A77970_CLK_ZTRD2		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define R8A77970_CLK_ZT			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define R8A77970_CLK_ZX			5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define R8A77970_CLK_S1D1		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define R8A77970_CLK_S1D2		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define R8A77970_CLK_S1D4		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define R8A77970_CLK_S2D1		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define R8A77970_CLK_S2D2		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define R8A77970_CLK_S2D4		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define R8A77970_CLK_LB			12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define R8A77970_CLK_CL			13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define R8A77970_CLK_ZB3		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define R8A77970_CLK_ZB3D2		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define R8A77970_CLK_DDR		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define R8A77970_CLK_CR			17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define R8A77970_CLK_CRD2		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define R8A77970_CLK_SD0H		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define R8A77970_CLK_SD0		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define R8A77970_CLK_RPC		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define R8A77970_CLK_RPCD2		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define R8A77970_CLK_MSO		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define R8A77970_CLK_CANFD		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define R8A77970_CLK_CSI0		25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define R8A77970_CLK_FRAY		26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define R8A77970_CLK_CP			27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define R8A77970_CLK_CPEX		28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define R8A77970_CLK_R			29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define R8A77970_CLK_OSC		30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #endif /* __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__ */