^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2014 Renesas Electronics Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 2013 Ideas On Board SPRL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef __DT_BINDINGS_CLOCK_R8A7794_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define __DT_BINDINGS_CLOCK_R8A7794_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /* CPG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define R8A7794_CLK_MAIN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define R8A7794_CLK_PLL0 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define R8A7794_CLK_PLL1 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define R8A7794_CLK_PLL3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define R8A7794_CLK_LB 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define R8A7794_CLK_QSPI 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define R8A7794_CLK_SDH 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define R8A7794_CLK_SD0 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define R8A7794_CLK_RCAN 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* MSTP0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define R8A7794_CLK_MSIOF0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* MSTP1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define R8A7794_CLK_VCP0 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define R8A7794_CLK_VPC0 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define R8A7794_CLK_TMU1 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define R8A7794_CLK_3DG 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define R8A7794_CLK_2DDMAC 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define R8A7794_CLK_FDP1_0 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define R8A7794_CLK_TMU3 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define R8A7794_CLK_TMU2 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define R8A7794_CLK_CMT0 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define R8A7794_CLK_TMU0 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define R8A7794_CLK_VSP1_DU0 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define R8A7794_CLK_VSP1_S 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* MSTP2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define R8A7794_CLK_SCIFA2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define R8A7794_CLK_SCIFA1 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define R8A7794_CLK_SCIFA0 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define R8A7794_CLK_MSIOF2 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define R8A7794_CLK_SCIFB0 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define R8A7794_CLK_SCIFB1 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define R8A7794_CLK_MSIOF1 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define R8A7794_CLK_SCIFB2 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define R8A7794_CLK_SYS_DMAC1 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define R8A7794_CLK_SYS_DMAC0 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* MSTP3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define R8A7794_CLK_SDHI2 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define R8A7794_CLK_SDHI1 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define R8A7794_CLK_SDHI0 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define R8A7794_CLK_MMCIF0 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define R8A7794_CLK_IIC0 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define R8A7794_CLK_IIC1 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define R8A7794_CLK_CMT1 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define R8A7794_CLK_USBDMAC0 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define R8A7794_CLK_USBDMAC1 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* MSTP4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define R8A7794_CLK_IRQC 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define R8A7794_CLK_INTC_SYS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* MSTP5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define R8A7794_CLK_AUDIO_DMAC0 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define R8A7794_CLK_PWM 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* MSTP7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define R8A7794_CLK_EHCI 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define R8A7794_CLK_HSUSB 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define R8A7794_CLK_HSCIF2 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define R8A7794_CLK_SCIF5 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define R8A7794_CLK_SCIF4 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define R8A7794_CLK_HSCIF1 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define R8A7794_CLK_HSCIF0 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define R8A7794_CLK_SCIF3 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define R8A7794_CLK_SCIF2 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define R8A7794_CLK_SCIF1 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define R8A7794_CLK_SCIF0 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define R8A7794_CLK_DU1 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define R8A7794_CLK_DU0 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* MSTP8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define R8A7794_CLK_VIN1 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define R8A7794_CLK_VIN0 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define R8A7794_CLK_ETHERAVB 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define R8A7794_CLK_ETHER 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* MSTP9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define R8A7794_CLK_GPIO6 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define R8A7794_CLK_GPIO5 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define R8A7794_CLK_GPIO4 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define R8A7794_CLK_GPIO3 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define R8A7794_CLK_GPIO2 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define R8A7794_CLK_GPIO1 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define R8A7794_CLK_GPIO0 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define R8A7794_CLK_RCAN1 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define R8A7794_CLK_RCAN0 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define R8A7794_CLK_QSPI_MOD 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define R8A7794_CLK_I2C5 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define R8A7794_CLK_I2C4 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define R8A7794_CLK_I2C3 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define R8A7794_CLK_I2C2 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define R8A7794_CLK_I2C1 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define R8A7794_CLK_I2C0 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* MSTP10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define R8A7794_CLK_SSI_ALL 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define R8A7794_CLK_SSI9 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define R8A7794_CLK_SSI8 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define R8A7794_CLK_SSI7 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define R8A7794_CLK_SSI6 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define R8A7794_CLK_SSI5 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define R8A7794_CLK_SSI4 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define R8A7794_CLK_SSI3 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define R8A7794_CLK_SSI2 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define R8A7794_CLK_SSI1 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define R8A7794_CLK_SSI0 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define R8A7794_CLK_SCU_ALL 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define R8A7794_CLK_SCU_DVC1 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define R8A7794_CLK_SCU_DVC0 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define R8A7794_CLK_SCU_CTU1_MIX1 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define R8A7794_CLK_SCU_CTU0_MIX0 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define R8A7794_CLK_SCU_SRC6 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define R8A7794_CLK_SCU_SRC5 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define R8A7794_CLK_SCU_SRC4 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define R8A7794_CLK_SCU_SRC3 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define R8A7794_CLK_SCU_SRC2 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define R8A7794_CLK_SCU_SRC1 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* MSTP11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define R8A7794_CLK_SCIFA3 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define R8A7794_CLK_SCIFA4 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define R8A7794_CLK_SCIFA5 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #endif /* __DT_BINDINGS_CLOCK_R8A7794_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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