Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (C) 2015 Renesas Electronics Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #ifndef __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <dt-bindings/clock/renesas-cpg-mssr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /* r8a7792 CPG Core Clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define R8A7792_CLK_Z			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define R8A7792_CLK_ZG			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define R8A7792_CLK_ZTR			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define R8A7792_CLK_ZTRD2		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define R8A7792_CLK_ZT			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define R8A7792_CLK_ZX			5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define R8A7792_CLK_ZS			6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define R8A7792_CLK_HP			7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define R8A7792_CLK_I			8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define R8A7792_CLK_B			9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define R8A7792_CLK_LB			10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define R8A7792_CLK_P			11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define R8A7792_CLK_CL			12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define R8A7792_CLK_M2			13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define R8A7792_CLK_IMP			14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define R8A7792_CLK_ZB3			15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define R8A7792_CLK_ZB3D2		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define R8A7792_CLK_DDR			17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define R8A7792_CLK_SD			18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define R8A7792_CLK_MP			19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define R8A7792_CLK_QSPI		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define R8A7792_CLK_CP			21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define R8A7792_CLK_CPEX		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define R8A7792_CLK_RCAN		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define R8A7792_CLK_R			24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define R8A7792_CLK_OSC			25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #endif /* __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__ */