^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2016 Cogent Embedded, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef __DT_BINDINGS_CLOCK_R8A7792_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define __DT_BINDINGS_CLOCK_R8A7792_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) /* CPG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define R8A7792_CLK_MAIN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define R8A7792_CLK_PLL0 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define R8A7792_CLK_PLL1 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define R8A7792_CLK_PLL3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define R8A7792_CLK_LB 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define R8A7792_CLK_QSPI 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* MSTP0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define R8A7792_CLK_MSIOF0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* MSTP1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define R8A7792_CLK_JPU 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define R8A7792_CLK_TMU1 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define R8A7792_CLK_TMU3 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define R8A7792_CLK_TMU2 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define R8A7792_CLK_CMT0 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define R8A7792_CLK_TMU0 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define R8A7792_CLK_VSP1DU1 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define R8A7792_CLK_VSP1DU0 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define R8A7792_CLK_VSP1_SY 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* MSTP2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define R8A7792_CLK_MSIOF1 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define R8A7792_CLK_SYS_DMAC1 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define R8A7792_CLK_SYS_DMAC0 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* MSTP3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define R8A7792_CLK_TPU0 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define R8A7792_CLK_SDHI0 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define R8A7792_CLK_CMT1 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* MSTP4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define R8A7792_CLK_IRQC 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define R8A7792_CLK_INTC_SYS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* MSTP5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define R8A7792_CLK_AUDIO_DMAC0 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define R8A7792_CLK_THERMAL 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define R8A7792_CLK_PWM 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* MSTP7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define R8A7792_CLK_HSCIF1 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define R8A7792_CLK_HSCIF0 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define R8A7792_CLK_SCIF3 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define R8A7792_CLK_SCIF2 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define R8A7792_CLK_SCIF1 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define R8A7792_CLK_SCIF0 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define R8A7792_CLK_DU1 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define R8A7792_CLK_DU0 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* MSTP8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define R8A7792_CLK_VIN5 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define R8A7792_CLK_VIN4 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define R8A7792_CLK_VIN3 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define R8A7792_CLK_VIN2 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define R8A7792_CLK_VIN1 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define R8A7792_CLK_VIN0 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define R8A7792_CLK_ETHERAVB 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* MSTP9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define R8A7792_CLK_GPIO7 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define R8A7792_CLK_GPIO6 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define R8A7792_CLK_GPIO5 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define R8A7792_CLK_GPIO4 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define R8A7792_CLK_GPIO3 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define R8A7792_CLK_GPIO2 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define R8A7792_CLK_GPIO1 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define R8A7792_CLK_GPIO0 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define R8A7792_CLK_GPIO11 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define R8A7792_CLK_GPIO10 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define R8A7792_CLK_CAN1 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define R8A7792_CLK_CAN0 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define R8A7792_CLK_QSPI_MOD 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define R8A7792_CLK_GPIO9 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define R8A7792_CLK_GPIO8 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define R8A7792_CLK_I2C5 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define R8A7792_CLK_IICDVFS 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define R8A7792_CLK_I2C4 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define R8A7792_CLK_I2C3 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define R8A7792_CLK_I2C2 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define R8A7792_CLK_I2C1 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define R8A7792_CLK_I2C0 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* MSTP10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define R8A7792_CLK_SSI_ALL 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define R8A7792_CLK_SSI4 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define R8A7792_CLK_SSI3 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #endif /* __DT_BINDINGS_CLOCK_R8A7792_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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