^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2013 Ideas On Board SPRL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef __DT_BINDINGS_CLOCK_R8A7790_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define __DT_BINDINGS_CLOCK_R8A7790_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) /* CPG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define R8A7790_CLK_MAIN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define R8A7790_CLK_PLL0 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define R8A7790_CLK_PLL1 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define R8A7790_CLK_PLL3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define R8A7790_CLK_LB 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define R8A7790_CLK_QSPI 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define R8A7790_CLK_SDH 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define R8A7790_CLK_SD0 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define R8A7790_CLK_SD1 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define R8A7790_CLK_Z 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define R8A7790_CLK_RCAN 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define R8A7790_CLK_ADSP 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* MSTP0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define R8A7790_CLK_MSIOF0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* MSTP1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define R8A7790_CLK_VCP1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define R8A7790_CLK_VCP0 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define R8A7790_CLK_VPC1 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define R8A7790_CLK_VPC0 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define R8A7790_CLK_JPU 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define R8A7790_CLK_SSP1 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define R8A7790_CLK_TMU1 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define R8A7790_CLK_3DG 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define R8A7790_CLK_2DDMAC 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define R8A7790_CLK_FDP1_2 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define R8A7790_CLK_FDP1_1 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define R8A7790_CLK_FDP1_0 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define R8A7790_CLK_TMU3 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define R8A7790_CLK_TMU2 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define R8A7790_CLK_CMT0 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define R8A7790_CLK_TMU0 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define R8A7790_CLK_VSP1_DU1 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define R8A7790_CLK_VSP1_DU0 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define R8A7790_CLK_VSP1_R 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define R8A7790_CLK_VSP1_S 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* MSTP2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define R8A7790_CLK_SCIFA2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define R8A7790_CLK_SCIFA1 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define R8A7790_CLK_SCIFA0 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define R8A7790_CLK_MSIOF2 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define R8A7790_CLK_SCIFB0 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define R8A7790_CLK_SCIFB1 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define R8A7790_CLK_MSIOF1 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define R8A7790_CLK_MSIOF3 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define R8A7790_CLK_SCIFB2 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define R8A7790_CLK_SYS_DMAC1 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define R8A7790_CLK_SYS_DMAC0 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* MSTP3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define R8A7790_CLK_IIC2 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define R8A7790_CLK_TPU0 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define R8A7790_CLK_MMCIF1 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define R8A7790_CLK_SCIF2 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define R8A7790_CLK_SDHI3 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define R8A7790_CLK_SDHI2 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define R8A7790_CLK_SDHI1 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define R8A7790_CLK_SDHI0 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define R8A7790_CLK_MMCIF0 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define R8A7790_CLK_IIC0 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define R8A7790_CLK_PCIEC 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define R8A7790_CLK_IIC1 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define R8A7790_CLK_SSUSB 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define R8A7790_CLK_CMT1 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define R8A7790_CLK_USBDMAC0 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define R8A7790_CLK_USBDMAC1 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* MSTP4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define R8A7790_CLK_IRQC 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define R8A7790_CLK_INTC_SYS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* MSTP5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define R8A7790_CLK_AUDIO_DMAC1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define R8A7790_CLK_AUDIO_DMAC0 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define R8A7790_CLK_ADSP_MOD 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define R8A7790_CLK_THERMAL 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define R8A7790_CLK_PWM 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* MSTP7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define R8A7790_CLK_EHCI 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define R8A7790_CLK_HSUSB 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define R8A7790_CLK_HSCIF1 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define R8A7790_CLK_HSCIF0 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define R8A7790_CLK_SCIF1 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define R8A7790_CLK_SCIF0 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define R8A7790_CLK_DU2 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define R8A7790_CLK_DU1 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define R8A7790_CLK_DU0 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define R8A7790_CLK_LVDS1 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define R8A7790_CLK_LVDS0 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* MSTP8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define R8A7790_CLK_MLB 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define R8A7790_CLK_VIN3 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define R8A7790_CLK_VIN2 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define R8A7790_CLK_VIN1 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define R8A7790_CLK_VIN0 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define R8A7790_CLK_ETHERAVB 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define R8A7790_CLK_ETHER 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define R8A7790_CLK_SATA1 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define R8A7790_CLK_SATA0 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* MSTP9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define R8A7790_CLK_GPIO5 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define R8A7790_CLK_GPIO4 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define R8A7790_CLK_GPIO3 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define R8A7790_CLK_GPIO2 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define R8A7790_CLK_GPIO1 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define R8A7790_CLK_GPIO0 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define R8A7790_CLK_RCAN1 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define R8A7790_CLK_RCAN0 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define R8A7790_CLK_QSPI_MOD 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define R8A7790_CLK_IICDVFS 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define R8A7790_CLK_I2C3 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define R8A7790_CLK_I2C2 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define R8A7790_CLK_I2C1 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define R8A7790_CLK_I2C0 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* MSTP10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define R8A7790_CLK_SSI_ALL 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define R8A7790_CLK_SSI9 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define R8A7790_CLK_SSI8 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define R8A7790_CLK_SSI7 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define R8A7790_CLK_SSI6 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define R8A7790_CLK_SSI5 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define R8A7790_CLK_SSI4 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define R8A7790_CLK_SSI3 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define R8A7790_CLK_SSI2 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define R8A7790_CLK_SSI1 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define R8A7790_CLK_SSI0 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define R8A7790_CLK_SCU_ALL 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define R8A7790_CLK_SCU_DVC1 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define R8A7790_CLK_SCU_DVC0 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define R8A7790_CLK_SCU_CTU1_MIX1 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define R8A7790_CLK_SCU_CTU0_MIX0 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define R8A7790_CLK_SCU_SRC9 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define R8A7790_CLK_SCU_SRC8 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define R8A7790_CLK_SCU_SRC7 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define R8A7790_CLK_SCU_SRC6 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define R8A7790_CLK_SCU_SRC5 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define R8A7790_CLK_SCU_SRC4 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define R8A7790_CLK_SCU_SRC3 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define R8A7790_CLK_SCU_SRC2 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define R8A7790_CLK_SCU_SRC1 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define R8A7790_CLK_SCU_SRC0 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #endif /* __DT_BINDINGS_CLOCK_R8A7790_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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