Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (C) 2014 Ulrich Hecht
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #ifndef __DT_BINDINGS_CLOCK_R8A7778_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define __DT_BINDINGS_CLOCK_R8A7778_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) /* CPG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define R8A7778_CLK_PLLA	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define R8A7778_CLK_PLLB	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define R8A7778_CLK_B		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define R8A7778_CLK_OUT		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define R8A7778_CLK_P		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define R8A7778_CLK_S		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define R8A7778_CLK_S1		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /* MSTP0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define R8A7778_CLK_I2C0	30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define R8A7778_CLK_I2C1	29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define R8A7778_CLK_I2C2	28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define R8A7778_CLK_I2C3	27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define R8A7778_CLK_SCIF0	26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define R8A7778_CLK_SCIF1	25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define R8A7778_CLK_SCIF2	24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define R8A7778_CLK_SCIF3	23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define R8A7778_CLK_SCIF4	22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define R8A7778_CLK_SCIF5	21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define R8A7778_CLK_HSCIF0	19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define R8A7778_CLK_HSCIF1	18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define R8A7778_CLK_TMU0	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define R8A7778_CLK_TMU1	15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define R8A7778_CLK_TMU2	14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define R8A7778_CLK_SSI0	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define R8A7778_CLK_SSI1	11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define R8A7778_CLK_SSI2	10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define R8A7778_CLK_SSI3	9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define R8A7778_CLK_SRU		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define R8A7778_CLK_HSPI	7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* MSTP1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define R8A7778_CLK_ETHER	14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define R8A7778_CLK_VIN0	10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define R8A7778_CLK_VIN1	9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define R8A7778_CLK_USB		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* MSTP3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define R8A7778_CLK_MMC		31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define R8A7778_CLK_SDHI0	23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define R8A7778_CLK_SDHI1	22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define R8A7778_CLK_SDHI2	21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define R8A7778_CLK_SSI4	11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define R8A7778_CLK_SSI5	10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define R8A7778_CLK_SSI6	9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define R8A7778_CLK_SSI7	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define R8A7778_CLK_SSI8	7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* MSTP5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define R8A7778_CLK_SRU_SRC0	31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define R8A7778_CLK_SRU_SRC1	30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define R8A7778_CLK_SRU_SRC2	29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define R8A7778_CLK_SRU_SRC3	28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define R8A7778_CLK_SRU_SRC4	27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define R8A7778_CLK_SRU_SRC5	26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define R8A7778_CLK_SRU_SRC6	25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define R8A7778_CLK_SRU_SRC7	24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define R8A7778_CLK_SRU_SRC8	23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #endif /* __DT_BINDINGS_CLOCK_R8A7778_H__ */