Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (C) 2018 Renesas Electronics Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) #ifndef __DT_BINDINGS_CLOCK_R8A774C0_CPG_MSSR_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #define __DT_BINDINGS_CLOCK_R8A774C0_CPG_MSSR_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <dt-bindings/clock/renesas-cpg-mssr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /* r8a774c0 CPG Core Clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define R8A774C0_CLK_Z2			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define R8A774C0_CLK_ZG			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define R8A774C0_CLK_ZTR		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define R8A774C0_CLK_ZT			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define R8A774C0_CLK_ZX			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define R8A774C0_CLK_S0D1		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define R8A774C0_CLK_S0D3		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define R8A774C0_CLK_S0D6		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define R8A774C0_CLK_S0D12		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define R8A774C0_CLK_S0D24		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define R8A774C0_CLK_S1D1		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define R8A774C0_CLK_S1D2		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define R8A774C0_CLK_S1D4		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define R8A774C0_CLK_S2D1		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define R8A774C0_CLK_S2D2		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define R8A774C0_CLK_S2D4		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define R8A774C0_CLK_S3D1		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define R8A774C0_CLK_S3D2		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define R8A774C0_CLK_S3D4		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define R8A774C0_CLK_S0D6C		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define R8A774C0_CLK_S3D1C		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define R8A774C0_CLK_S3D2C		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define R8A774C0_CLK_S3D4C		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define R8A774C0_CLK_LB			23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define R8A774C0_CLK_CL			24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define R8A774C0_CLK_ZB3		25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define R8A774C0_CLK_ZB3D2		26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define R8A774C0_CLK_CR			27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define R8A774C0_CLK_CRD2		28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define R8A774C0_CLK_SD0H		29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define R8A774C0_CLK_SD0		30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define R8A774C0_CLK_SD1H		31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define R8A774C0_CLK_SD1		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define R8A774C0_CLK_SD3H		33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define R8A774C0_CLK_SD3		34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define R8A774C0_CLK_RPC		35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define R8A774C0_CLK_RPCD2		36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define R8A774C0_CLK_ZA2		37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define R8A774C0_CLK_ZA8		38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define R8A774C0_CLK_Z2D		39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define R8A774C0_CLK_MSO		40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define R8A774C0_CLK_R			41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define R8A774C0_CLK_OSC		42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define R8A774C0_CLK_LV0		43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define R8A774C0_CLK_LV1		44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define R8A774C0_CLK_CSI0		45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define R8A774C0_CLK_CP			46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define R8A774C0_CLK_CPEX		47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define R8A774C0_CLK_CANFD		48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #endif /* __DT_BINDINGS_CLOCK_R8A774C0_CPG_MSSR_H__ */