Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (C) 2018 Renesas Electronics Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) #ifndef __DT_BINDINGS_CLOCK_R8A77470_CPG_MSSR_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #define __DT_BINDINGS_CLOCK_R8A77470_CPG_MSSR_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <dt-bindings/clock/renesas-cpg-mssr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /* r8a77470 CPG Core Clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define R8A77470_CLK_Z2		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define R8A77470_CLK_ZTR	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define R8A77470_CLK_ZTRD2	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define R8A77470_CLK_ZT		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define R8A77470_CLK_ZX		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define R8A77470_CLK_ZS		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define R8A77470_CLK_HP		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define R8A77470_CLK_B		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define R8A77470_CLK_LB		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define R8A77470_CLK_P		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define R8A77470_CLK_CL		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define R8A77470_CLK_CP		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define R8A77470_CLK_M2		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define R8A77470_CLK_ZB3	13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define R8A77470_CLK_SDH	14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define R8A77470_CLK_SD0	15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define R8A77470_CLK_SD1	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define R8A77470_CLK_SD2	17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define R8A77470_CLK_MP		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define R8A77470_CLK_QSPI	19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define R8A77470_CLK_CPEX	20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define R8A77470_CLK_RCAN	21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define R8A77470_CLK_R		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define R8A77470_CLK_OSC	23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #endif /* __DT_BINDINGS_CLOCK_R8A77470_CPG_MSSR_H__ */