Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (C) 2016 Cogent Embedded Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) #ifndef __DT_BINDINGS_CLOCK_R8A7745_CPG_MSSR_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #define __DT_BINDINGS_CLOCK_R8A7745_CPG_MSSR_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <dt-bindings/clock/renesas-cpg-mssr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /* r8a7745 CPG Core Clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define R8A7745_CLK_Z2		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define R8A7745_CLK_ZG		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define R8A7745_CLK_ZTR		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define R8A7745_CLK_ZTRD2	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define R8A7745_CLK_ZT		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define R8A7745_CLK_ZX		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define R8A7745_CLK_ZS		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define R8A7745_CLK_HP		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define R8A7745_CLK_B		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define R8A7745_CLK_LB		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define R8A7745_CLK_P		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define R8A7745_CLK_CL		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define R8A7745_CLK_CP		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define R8A7745_CLK_M2		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define R8A7745_CLK_ZB3		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define R8A7745_CLK_ZB3D2	17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define R8A7745_CLK_DDR		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define R8A7745_CLK_SDH		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define R8A7745_CLK_SD0		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define R8A7745_CLK_SD2		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define R8A7745_CLK_SD3		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define R8A7745_CLK_MMC0	23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define R8A7745_CLK_MP		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define R8A7745_CLK_QSPI	25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define R8A7745_CLK_CPEX	26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define R8A7745_CLK_RCAN	27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define R8A7745_CLK_R		28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define R8A7745_CLK_OSC		29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #endif /* __DT_BINDINGS_CLOCK_R8A7745_CPG_MSSR_H__ */