Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright 2014 Ulrich Hecht
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #ifndef __DT_BINDINGS_CLOCK_R8A7740_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define __DT_BINDINGS_CLOCK_R8A7740_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) /* CPG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define R8A7740_CLK_SYSTEM	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define R8A7740_CLK_PLLC0	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define R8A7740_CLK_PLLC1	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define R8A7740_CLK_PLLC2	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define R8A7740_CLK_R		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define R8A7740_CLK_USB24S	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define R8A7740_CLK_I		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define R8A7740_CLK_ZG		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define R8A7740_CLK_B		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define R8A7740_CLK_M1		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define R8A7740_CLK_HP		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define R8A7740_CLK_HPP		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define R8A7740_CLK_USBP	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define R8A7740_CLK_S		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define R8A7740_CLK_ZB		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define R8A7740_CLK_M3		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define R8A7740_CLK_CP		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* MSTP1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define R8A7740_CLK_CEU21	28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define R8A7740_CLK_CEU20	27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define R8A7740_CLK_TMU0	25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define R8A7740_CLK_LCDC1	17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define R8A7740_CLK_IIC0	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define R8A7740_CLK_TMU1	11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define R8A7740_CLK_LCDC0	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* MSTP2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define R8A7740_CLK_SCIFA6	30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define R8A7740_CLK_INTCA	29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define R8A7740_CLK_SCIFA7	22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define R8A7740_CLK_DMAC1	18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define R8A7740_CLK_DMAC2	17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define R8A7740_CLK_DMAC3	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define R8A7740_CLK_USBDMAC	14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define R8A7740_CLK_SCIFA5	7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define R8A7740_CLK_SCIFB	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define R8A7740_CLK_SCIFA0	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define R8A7740_CLK_SCIFA1	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define R8A7740_CLK_SCIFA2	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define R8A7740_CLK_SCIFA3	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define R8A7740_CLK_SCIFA4	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* MSTP3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define R8A7740_CLK_CMT1	29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define R8A7740_CLK_FSI		28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define R8A7740_CLK_IIC1	23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define R8A7740_CLK_USBF	20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define R8A7740_CLK_SDHI0	14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define R8A7740_CLK_SDHI1	13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define R8A7740_CLK_MMC		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define R8A7740_CLK_GETHER	9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define R8A7740_CLK_TPU0	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* MSTP4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define R8A7740_CLK_USBH	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define R8A7740_CLK_SDHI2	15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define R8A7740_CLK_USBFUNC	7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define R8A7740_CLK_USBPHY	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* SUBCK* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define R8A7740_CLK_SUBCK	9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define R8A7740_CLK_SUBCK2	10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #endif /* __DT_BINDINGS_CLOCK_R8A7740_H__ */