Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright 2014 Ulrich Hecht
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #ifndef __DT_BINDINGS_CLOCK_R8A73A4_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define __DT_BINDINGS_CLOCK_R8A73A4_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) /* CPG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define R8A73A4_CLK_MAIN	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define R8A73A4_CLK_PLL0	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define R8A73A4_CLK_PLL1	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define R8A73A4_CLK_PLL2	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define R8A73A4_CLK_PLL2S	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define R8A73A4_CLK_PLL2H	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define R8A73A4_CLK_Z		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define R8A73A4_CLK_Z2		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define R8A73A4_CLK_I		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define R8A73A4_CLK_M3		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define R8A73A4_CLK_B		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define R8A73A4_CLK_M1		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define R8A73A4_CLK_M2		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define R8A73A4_CLK_ZX		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define R8A73A4_CLK_ZS		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define R8A73A4_CLK_HP		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* MSTP2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define R8A73A4_CLK_DMAC	18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define R8A73A4_CLK_SCIFB3	17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define R8A73A4_CLK_SCIFB2	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define R8A73A4_CLK_SCIFB1	7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define R8A73A4_CLK_SCIFB0	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define R8A73A4_CLK_SCIFA0	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define R8A73A4_CLK_SCIFA1	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* MSTP3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define R8A73A4_CLK_CMT1	29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define R8A73A4_CLK_IIC1	23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define R8A73A4_CLK_IIC0	18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define R8A73A4_CLK_IIC7	17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define R8A73A4_CLK_IIC6	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define R8A73A4_CLK_MMCIF0	15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define R8A73A4_CLK_SDHI0	14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define R8A73A4_CLK_SDHI1	13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define R8A73A4_CLK_SDHI2	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define R8A73A4_CLK_MMCIF1	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define R8A73A4_CLK_IIC2	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* MSTP4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define R8A73A4_CLK_IIC3	11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define R8A73A4_CLK_IIC4	10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define R8A73A4_CLK_IIC5	9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define R8A73A4_CLK_INTC_SYS	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define R8A73A4_CLK_IRQC	7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* MSTP5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define R8A73A4_CLK_THERMAL	22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define R8A73A4_CLK_IIC8	15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #endif /* __DT_BINDINGS_CLOCK_R8A73A4_H__ */