^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2018 Renesas Electronics Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef __DT_BINDINGS_CLOCK_R7S9210_CPG_MSSR_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define __DT_BINDINGS_CLOCK_R7S9210_CPG_MSSR_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <dt-bindings/clock/renesas-cpg-mssr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /* R7S9210 CPG Core Clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define R7S9210_CLK_I 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define R7S9210_CLK_G 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define R7S9210_CLK_B 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define R7S9210_CLK_P1 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define R7S9210_CLK_P1C 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define R7S9210_CLK_P0 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #endif /* __DT_BINDINGS_CLOCK_R7S9210_CPG_MSSR_H__ */