^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2014 Renesas Solutions Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef __DT_BINDINGS_CLOCK_R7S72100_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define __DT_BINDINGS_CLOCK_R7S72100_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define R7S72100_CLK_PLL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define R7S72100_CLK_I 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define R7S72100_CLK_G 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /* MSTP2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define R7S72100_CLK_CORESIGHT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* MSTP3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define R7S72100_CLK_IEBUS 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define R7S72100_CLK_IRDA 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define R7S72100_CLK_LIN0 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define R7S72100_CLK_LIN1 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define R7S72100_CLK_MTU2 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define R7S72100_CLK_CAN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define R7S72100_CLK_ADCPWR 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define R7S72100_CLK_PWM 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* MSTP4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define R7S72100_CLK_SCIF0 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define R7S72100_CLK_SCIF1 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define R7S72100_CLK_SCIF2 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define R7S72100_CLK_SCIF3 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define R7S72100_CLK_SCIF4 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define R7S72100_CLK_SCIF5 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define R7S72100_CLK_SCIF6 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define R7S72100_CLK_SCIF7 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* MSTP5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define R7S72100_CLK_SCI0 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define R7S72100_CLK_SCI1 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define R7S72100_CLK_SG0 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define R7S72100_CLK_SG1 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define R7S72100_CLK_SG2 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define R7S72100_CLK_SG3 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define R7S72100_CLK_OSTM0 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define R7S72100_CLK_OSTM1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* MSTP6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define R7S72100_CLK_ADC 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define R7S72100_CLK_CEU 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define R7S72100_CLK_DOC0 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define R7S72100_CLK_DOC1 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define R7S72100_CLK_DRC0 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define R7S72100_CLK_DRC1 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define R7S72100_CLK_JCU 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define R7S72100_CLK_RTC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* MSTP7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define R7S72100_CLK_VDEC0 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define R7S72100_CLK_VDEC1 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define R7S72100_CLK_ETHER 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define R7S72100_CLK_NAND 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define R7S72100_CLK_USB0 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define R7S72100_CLK_USB1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* MSTP8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define R7S72100_CLK_IMR0 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define R7S72100_CLK_IMR1 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define R7S72100_CLK_IMRDISP 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define R7S72100_CLK_MMCIF 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define R7S72100_CLK_MLB 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define R7S72100_CLK_ETHAVB 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define R7S72100_CLK_SCUX 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* MSTP9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define R7S72100_CLK_I2C0 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define R7S72100_CLK_I2C1 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define R7S72100_CLK_I2C2 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define R7S72100_CLK_I2C3 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define R7S72100_CLK_SPIBSC0 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define R7S72100_CLK_SPIBSC1 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define R7S72100_CLK_VDC50 1 /* and LVDS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define R7S72100_CLK_VDC51 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* MSTP10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define R7S72100_CLK_SPI0 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define R7S72100_CLK_SPI1 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define R7S72100_CLK_SPI2 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define R7S72100_CLK_SPI3 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define R7S72100_CLK_SPI4 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define R7S72100_CLK_CDROM 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define R7S72100_CLK_SPDIF 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define R7S72100_CLK_RGPVG2 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* MSTP11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define R7S72100_CLK_SSI0 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define R7S72100_CLK_SSI1 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define R7S72100_CLK_SSI2 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define R7S72100_CLK_SSI3 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define R7S72100_CLK_SSI4 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define R7S72100_CLK_SSI5 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* MSTP12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define R7S72100_CLK_SDHI00 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define R7S72100_CLK_SDHI01 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define R7S72100_CLK_SDHI10 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define R7S72100_CLK_SDHI11 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* MSTP13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define R7S72100_CLK_PIX1 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define R7S72100_CLK_PIX0 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #endif /* __DT_BINDINGS_CLOCK_R7S72100_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags