^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8250_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8250_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) /* VIDEO_CC clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define VIDEO_CC_MVS0_CLK_SRC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define VIDEO_CC_MVS0C_CLK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define VIDEO_CC_MVS1_CLK_SRC 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define VIDEO_CC_MVS1_DIV2_CLK 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define VIDEO_CC_MVS1C_CLK 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define VIDEO_CC_PLL0 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define VIDEO_CC_PLL1 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* VIDEO_CC resets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define VIDEO_CC_CVP_INTERFACE_BCR 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define VIDEO_CC_CVP_MVS0_BCR 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define VIDEO_CC_MVS0C_CLK_ARES 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define VIDEO_CC_CVP_MVS0C_BCR 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define VIDEO_CC_CVP_MVS1_BCR 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define VIDEO_CC_MVS1C_CLK_ARES 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define VIDEO_CC_CVP_MVS1C_BCR 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MVS0C_GDSC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MVS1C_GDSC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MVS0_GDSC 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MVS1_GDSC 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #endif