Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (c) 2018, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #ifndef _DT_BINDINGS_CLK_SDM_VIDEO_CC_SDM845_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define _DT_BINDINGS_CLK_SDM_VIDEO_CC_SDM845_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) /* VIDEO_CC clock registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define VIDEO_CC_APB_CLK		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define VIDEO_CC_AT_CLK			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define VIDEO_CC_QDSS_TRIG_CLK		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define VIDEO_CC_QDSS_TSCTR_DIV8_CLK	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define VIDEO_CC_VCODEC0_AXI_CLK	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define VIDEO_CC_VCODEC0_CORE_CLK	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define VIDEO_CC_VCODEC1_AXI_CLK	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define VIDEO_CC_VCODEC1_CORE_CLK	7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define VIDEO_CC_VENUS_AHB_CLK		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define VIDEO_CC_VENUS_CLK_SRC		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define VIDEO_CC_VENUS_CTL_AXI_CLK	10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define VIDEO_CC_VENUS_CTL_CORE_CLK	11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define VIDEO_PLL0			12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* VIDEO_CC Resets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define VIDEO_CC_VENUS_BCR		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define VIDEO_CC_VCODEC0_BCR		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define VIDEO_CC_VCODEC1_BCR		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define VIDEO_CC_INTERFACE_BCR		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* VIDEO_CC GDSCRs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define VENUS_GDSC			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define VCODEC0_GDSC			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define VCODEC1_GDSC			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #endif