^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2015 Linaro Limited
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef _DT_BINDINGS_CLK_MSM_RPMCC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define _DT_BINDINGS_CLK_MSM_RPMCC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) /* RPM clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define RPM_PXO_CLK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define RPM_PXO_A_CLK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define RPM_CXO_CLK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define RPM_CXO_A_CLK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define RPM_APPS_FABRIC_CLK 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define RPM_APPS_FABRIC_A_CLK 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define RPM_CFPB_CLK 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define RPM_CFPB_A_CLK 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define RPM_QDSS_CLK 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define RPM_QDSS_A_CLK 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define RPM_DAYTONA_FABRIC_CLK 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define RPM_DAYTONA_FABRIC_A_CLK 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define RPM_EBI1_CLK 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define RPM_EBI1_A_CLK 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define RPM_MM_FABRIC_CLK 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define RPM_MM_FABRIC_A_CLK 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define RPM_MMFPB_CLK 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define RPM_MMFPB_A_CLK 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define RPM_SYS_FABRIC_CLK 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define RPM_SYS_FABRIC_A_CLK 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define RPM_SFPB_CLK 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define RPM_SFPB_A_CLK 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define RPM_SMI_CLK 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define RPM_SMI_A_CLK 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define RPM_PLL4_CLK 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define RPM_XO_D0 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define RPM_XO_D1 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define RPM_XO_A0 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define RPM_XO_A1 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define RPM_XO_A2 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define RPM_NSS_FABRIC_0_CLK 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define RPM_NSS_FABRIC_0_A_CLK 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define RPM_NSS_FABRIC_1_CLK 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define RPM_NSS_FABRIC_1_A_CLK 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* SMD RPM clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define RPM_SMD_XO_CLK_SRC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define RPM_SMD_XO_A_CLK_SRC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define RPM_SMD_PCNOC_CLK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define RPM_SMD_PCNOC_A_CLK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define RPM_SMD_SNOC_CLK 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define RPM_SMD_SNOC_A_CLK 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define RPM_SMD_BIMC_CLK 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define RPM_SMD_BIMC_A_CLK 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define RPM_SMD_QDSS_CLK 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define RPM_SMD_QDSS_A_CLK 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define RPM_SMD_BB_CLK1 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define RPM_SMD_BB_CLK1_A 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define RPM_SMD_BB_CLK2 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define RPM_SMD_BB_CLK2_A 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define RPM_SMD_RF_CLK1 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define RPM_SMD_RF_CLK1_A 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define RPM_SMD_RF_CLK2 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define RPM_SMD_RF_CLK2_A 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define RPM_SMD_BB_CLK1_PIN 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define RPM_SMD_BB_CLK1_A_PIN 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define RPM_SMD_BB_CLK2_PIN 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define RPM_SMD_BB_CLK2_A_PIN 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define RPM_SMD_RF_CLK1_PIN 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define RPM_SMD_RF_CLK1_A_PIN 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define RPM_SMD_RF_CLK2_PIN 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define RPM_SMD_RF_CLK2_A_PIN 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define RPM_SMD_PNOC_CLK 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define RPM_SMD_PNOC_A_CLK 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define RPM_SMD_CNOC_CLK 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define RPM_SMD_CNOC_A_CLK 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define RPM_SMD_MMSSNOC_AHB_CLK 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define RPM_SMD_MMSSNOC_AHB_A_CLK 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define RPM_SMD_GFX3D_CLK_SRC 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define RPM_SMD_GFX3D_A_CLK_SRC 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define RPM_SMD_OCMEMGX_CLK 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define RPM_SMD_OCMEMGX_A_CLK 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define RPM_SMD_CXO_D0 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define RPM_SMD_CXO_D0_A 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define RPM_SMD_CXO_D1 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define RPM_SMD_CXO_D1_A 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define RPM_SMD_CXO_A0 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define RPM_SMD_CXO_A0_A 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define RPM_SMD_CXO_A1 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define RPM_SMD_CXO_A1_A 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define RPM_SMD_CXO_A2 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define RPM_SMD_CXO_A2_A 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define RPM_SMD_DIV_CLK1 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define RPM_SMD_DIV_A_CLK1 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define RPM_SMD_DIV_CLK2 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define RPM_SMD_DIV_A_CLK2 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define RPM_SMD_DIFF_CLK 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define RPM_SMD_DIFF_A_CLK 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define RPM_SMD_CXO_D0_PIN 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define RPM_SMD_CXO_D0_A_PIN 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define RPM_SMD_CXO_D1_PIN 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define RPM_SMD_CXO_D1_A_PIN 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define RPM_SMD_CXO_A0_PIN 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define RPM_SMD_CXO_A0_A_PIN 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define RPM_SMD_CXO_A1_PIN 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define RPM_SMD_CXO_A1_A_PIN 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define RPM_SMD_CXO_A2_PIN 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define RPM_SMD_CXO_A2_A_PIN 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define RPM_SMD_AGGR1_NOC_CLK 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define RPM_SMD_AGGR1_NOC_A_CLK 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define RPM_SMD_AGGR2_NOC_CLK 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define RPM_SMD_AGGR2_NOC_A_CLK 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define RPM_SMD_MMAXI_CLK 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define RPM_SMD_MMAXI_A_CLK 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define RPM_SMD_IPA_CLK 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define RPM_SMD_IPA_A_CLK 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define RPM_SMD_CE1_CLK 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define RPM_SMD_CE1_A_CLK 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define RPM_SMD_DIV_CLK3 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define RPM_SMD_DIV_A_CLK3 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define RPM_SMD_LN_BB_CLK 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define RPM_SMD_LN_BB_A_CLK 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define RPM_SMD_BIMC_GPU_CLK 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define RPM_SMD_BIMC_GPU_A_CLK 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define RPM_SMD_QPIC_CLK 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define RPM_SMD_QPIC_CLK_A 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define RPM_SMD_LN_BB_CLK1 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define RPM_SMD_LN_BB_CLK1_A 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define RPM_SMD_LN_BB_CLK2 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define RPM_SMD_LN_BB_CLK2_A 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define RPM_SMD_LN_BB_CLK3_PIN 84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define RPM_SMD_LN_BB_CLK3_A_PIN 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define RPM_SMD_RF_CLK3 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define RPM_SMD_RF_CLK3_A 87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define RPM_SMD_RF_CLK3_PIN 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define RPM_SMD_RF_CLK3_A_PIN 89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define RPM_SMD_MMSSNOC_AXI_CLK 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define RPM_SMD_MMSSNOC_AXI_CLK_A 91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define RPM_SMD_CNOC_PERIPH_CLK 92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define RPM_SMD_CNOC_PERIPH_A_CLK 93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define RPM_SMD_LN_BB_CLK3 94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define RPM_SMD_LN_BB_CLK3_A 95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define RPM_SMD_LN_BB_CLK1_PIN 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define RPM_SMD_LN_BB_CLK1_A_PIN 97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define RPM_SMD_LN_BB_CLK2_PIN 98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define RPM_SMD_LN_BB_CLK2_A_PIN 99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define RPM_SMD_SYSMMNOC_CLK 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define RPM_SMD_SYSMMNOC_A_CLK 101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define RPM_SMD_CE2_CLK 102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define RPM_SMD_CE2_A_CLK 103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define RPM_SMD_CE3_CLK 104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define RPM_SMD_CE3_A_CLK 105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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