Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2019, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #ifndef _DT_BINDINGS_CLK_MSM_MMCC_8998_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #define _DT_BINDINGS_CLK_MSM_MMCC_8998_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #define MMPLL0						0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #define MMPLL0_OUT_EVEN					1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define MMPLL1						2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define MMPLL1_OUT_EVEN					3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define MMPLL3						4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define MMPLL3_OUT_EVEN					5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define MMPLL4						6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define MMPLL4_OUT_EVEN					7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define MMPLL5						8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define MMPLL5_OUT_EVEN					9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define MMPLL6						10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define MMPLL6_OUT_EVEN					11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define MMPLL7						12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define MMPLL7_OUT_EVEN					13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define MMPLL10						14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define MMPLL10_OUT_EVEN				15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define BYTE0_CLK_SRC					16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define BYTE1_CLK_SRC					17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define CCI_CLK_SRC					18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define CPP_CLK_SRC					19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define CSI0_CLK_SRC					20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define CSI1_CLK_SRC					21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define CSI2_CLK_SRC					22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define CSI3_CLK_SRC					23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define CSIPHY_CLK_SRC					24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define CSI0PHYTIMER_CLK_SRC				25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define CSI1PHYTIMER_CLK_SRC				26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define CSI2PHYTIMER_CLK_SRC				27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define DP_AUX_CLK_SRC					28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define DP_CRYPTO_CLK_SRC				29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define DP_LINK_CLK_SRC					30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define DP_PIXEL_CLK_SRC				31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define ESC0_CLK_SRC					32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define ESC1_CLK_SRC					33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define EXTPCLK_CLK_SRC					34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define FD_CORE_CLK_SRC					35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define HDMI_CLK_SRC					36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define JPEG0_CLK_SRC					37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define MAXI_CLK_SRC					38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define MCLK0_CLK_SRC					39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define MCLK1_CLK_SRC					40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define MCLK2_CLK_SRC					41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define MCLK3_CLK_SRC					42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define MDP_CLK_SRC					43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define VSYNC_CLK_SRC					44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define AHB_CLK_SRC					45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define AXI_CLK_SRC					46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define PCLK0_CLK_SRC					47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define PCLK1_CLK_SRC					48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define ROT_CLK_SRC					49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define VIDEO_CORE_CLK_SRC				50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define VIDEO_SUBCORE0_CLK_SRC				51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define VIDEO_SUBCORE1_CLK_SRC				52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define VFE0_CLK_SRC					53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define VFE1_CLK_SRC					54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define MISC_AHB_CLK					55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define VIDEO_CORE_CLK					56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define VIDEO_AHB_CLK					57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define VIDEO_AXI_CLK					58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define VIDEO_MAXI_CLK					59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define VIDEO_SUBCORE0_CLK				60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define VIDEO_SUBCORE1_CLK				61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define MDSS_AHB_CLK					62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define MDSS_HDMI_DP_AHB_CLK				63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define MDSS_AXI_CLK					64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define MDSS_PCLK0_CLK					65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define MDSS_PCLK1_CLK					66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define MDSS_MDP_CLK					67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define MDSS_MDP_LUT_CLK				68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define MDSS_EXTPCLK_CLK				69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define MDSS_VSYNC_CLK					70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define MDSS_HDMI_CLK					71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define MDSS_BYTE0_CLK					72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define MDSS_BYTE1_CLK					73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define MDSS_ESC0_CLK					74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define MDSS_ESC1_CLK					75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define MDSS_ROT_CLK					76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define MDSS_DP_LINK_CLK				77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define MDSS_DP_LINK_INTF_CLK				78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define MDSS_DP_CRYPTO_CLK				79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define MDSS_DP_PIXEL_CLK				80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define MDSS_DP_AUX_CLK					81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define MDSS_BYTE0_INTF_CLK				82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define MDSS_BYTE1_INTF_CLK				83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define CAMSS_CSI0PHYTIMER_CLK				84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define CAMSS_CSI1PHYTIMER_CLK				85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define CAMSS_CSI2PHYTIMER_CLK				86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define CAMSS_CSI0_CLK					87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define CAMSS_CSI0_AHB_CLK				88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define CAMSS_CSI0RDI_CLK				89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define CAMSS_CSI0PIX_CLK				90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define CAMSS_CSI1_CLK					91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define CAMSS_CSI1_AHB_CLK				92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define CAMSS_CSI1RDI_CLK				93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define CAMSS_CSI1PIX_CLK				94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define CAMSS_CSI2_CLK					95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define CAMSS_CSI2_AHB_CLK				96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define CAMSS_CSI2RDI_CLK				97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define CAMSS_CSI2PIX_CLK				98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define CAMSS_CSI3_CLK					99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define CAMSS_CSI3_AHB_CLK				100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define CAMSS_CSI3RDI_CLK				101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define CAMSS_CSI3PIX_CLK				102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define CAMSS_ISPIF_AHB_CLK				103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define CAMSS_CCI_CLK					104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define CAMSS_CCI_AHB_CLK				105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define CAMSS_MCLK0_CLK					106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define CAMSS_MCLK1_CLK					107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define CAMSS_MCLK2_CLK					108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define CAMSS_MCLK3_CLK					109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define CAMSS_TOP_AHB_CLK				110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define CAMSS_AHB_CLK					111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define CAMSS_MICRO_AHB_CLK				112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define CAMSS_JPEG0_CLK					113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define CAMSS_JPEG_AHB_CLK				114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define CAMSS_JPEG_AXI_CLK				115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define CAMSS_VFE0_AHB_CLK				116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define CAMSS_VFE1_AHB_CLK				117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define CAMSS_VFE0_CLK					118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define CAMSS_VFE1_CLK					119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define CAMSS_CPP_CLK					120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define CAMSS_CPP_AHB_CLK				121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define CAMSS_VFE_VBIF_AHB_CLK				122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define CAMSS_VFE_VBIF_AXI_CLK				123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define CAMSS_CPP_AXI_CLK				124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define CAMSS_CPP_VBIF_AHB_CLK				125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define CAMSS_CSI_VFE0_CLK				126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define CAMSS_CSI_VFE1_CLK				127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define CAMSS_VFE0_STREAM_CLK				128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define CAMSS_VFE1_STREAM_CLK				129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define CAMSS_CPHY_CSID0_CLK				130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define CAMSS_CPHY_CSID1_CLK				131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define CAMSS_CPHY_CSID2_CLK				132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define CAMSS_CPHY_CSID3_CLK				133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define CAMSS_CSIPHY0_CLK				134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define CAMSS_CSIPHY1_CLK				135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define CAMSS_CSIPHY2_CLK				136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define FD_CORE_CLK					137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define FD_CORE_UAR_CLK					138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define FD_AHB_CLK					139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define MNOC_AHB_CLK					140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define BIMC_SMMU_AHB_CLK				141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define BIMC_SMMU_AXI_CLK				142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define MNOC_MAXI_CLK					143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define VMEM_MAXI_CLK					144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define VMEM_AHB_CLK					145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define SPDM_BCR					0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define SPDM_RM_BCR					1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define MISC_BCR					2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define VIDEO_TOP_BCR					3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define THROTTLE_VIDEO_BCR				4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define MDSS_BCR					5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define THROTTLE_MDSS_BCR				6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define CAMSS_PHY0_BCR					7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define CAMSS_PHY1_BCR					8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define CAMSS_PHY2_BCR					9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define CAMSS_CSI0_BCR					10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define CAMSS_CSI0RDI_BCR				11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define CAMSS_CSI0PIX_BCR				12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define CAMSS_CSI1_BCR					13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define CAMSS_CSI1RDI_BCR				14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define CAMSS_CSI1PIX_BCR				15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define CAMSS_CSI2_BCR					16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define CAMSS_CSI2RDI_BCR				17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define CAMSS_CSI2PIX_BCR				18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define CAMSS_CSI3_BCR					19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define CAMSS_CSI3RDI_BCR				20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define CAMSS_CSI3PIX_BCR				21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define CAMSS_ISPIF_BCR					22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define CAMSS_CCI_BCR					23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define CAMSS_TOP_BCR					24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define CAMSS_AHB_BCR					25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define CAMSS_MICRO_BCR					26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define CAMSS_JPEG_BCR					27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define CAMSS_VFE0_BCR					28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define CAMSS_VFE1_BCR					29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define CAMSS_VFE_VBIF_BCR				30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define CAMSS_CPP_TOP_BCR				31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define CAMSS_CPP_BCR					32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define CAMSS_CSI_VFE0_BCR				33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define CAMSS_CSI_VFE1_BCR				34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define CAMSS_FD_BCR					35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define THROTTLE_CAMSS_BCR				36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define MNOCAHB_BCR					37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define MNOCAXI_BCR					38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define BMIC_SMMU_BCR					39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define MNOC_MAXI_BCR					40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define VMEM_BCR					41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define BTO_BCR						42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define VIDEO_TOP_GDSC		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define VIDEO_SUBCORE0_GDSC	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define VIDEO_SUBCORE1_GDSC	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define MDSS_GDSC		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define CAMSS_TOP_GDSC		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define CAMSS_VFE0_GDSC		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define CAMSS_VFE1_GDSC		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define CAMSS_CPP_GDSC		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define BIMC_SMMU_GDSC		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #endif