Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2015, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #ifndef _DT_BINDINGS_CLK_MSM_MMCC_8996_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #define _DT_BINDINGS_CLK_MSM_MMCC_8996_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #define MMPLL0_EARLY					0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #define MMPLL0_PLL					1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define MMPLL1_EARLY					2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define MMPLL1_PLL					3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define MMPLL2_EARLY					4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define MMPLL2_PLL					5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define MMPLL3_EARLY					6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define MMPLL3_PLL					7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define MMPLL4_EARLY					8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define MMPLL4_PLL					9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define MMPLL5_EARLY					10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define MMPLL5_PLL					11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define MMPLL8_EARLY					12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define MMPLL8_PLL					13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define MMPLL9_EARLY					14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define MMPLL9_PLL					15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define AHB_CLK_SRC					16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define AXI_CLK_SRC					17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define MAXI_CLK_SRC					18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define DSA_CORE_CLK_SRC				19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define GFX3D_CLK_SRC					20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define RBBMTIMER_CLK_SRC				21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define ISENSE_CLK_SRC					22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define RBCPR_CLK_SRC					23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define VIDEO_CORE_CLK_SRC				24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define VIDEO_SUBCORE0_CLK_SRC				25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define VIDEO_SUBCORE1_CLK_SRC				26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define PCLK0_CLK_SRC					27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define PCLK1_CLK_SRC					28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define MDP_CLK_SRC					29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define EXTPCLK_CLK_SRC					30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define VSYNC_CLK_SRC					31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define HDMI_CLK_SRC					32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define BYTE0_CLK_SRC					33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define BYTE1_CLK_SRC					34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define ESC0_CLK_SRC					35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define ESC1_CLK_SRC					36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define CAMSS_GP0_CLK_SRC				37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define CAMSS_GP1_CLK_SRC				38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define MCLK0_CLK_SRC					39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define MCLK1_CLK_SRC					40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define MCLK2_CLK_SRC					41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define MCLK3_CLK_SRC					42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define CCI_CLK_SRC					43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define CSI0PHYTIMER_CLK_SRC				44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define CSI1PHYTIMER_CLK_SRC				45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define CSI2PHYTIMER_CLK_SRC				46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define CSIPHY0_3P_CLK_SRC				47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define CSIPHY1_3P_CLK_SRC				48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define CSIPHY2_3P_CLK_SRC				49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define JPEG0_CLK_SRC					50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define JPEG2_CLK_SRC					51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define JPEG_DMA_CLK_SRC				52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define VFE0_CLK_SRC					53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define VFE1_CLK_SRC					54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define CPP_CLK_SRC					55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define CSI0_CLK_SRC					56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define CSI1_CLK_SRC					57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define CSI2_CLK_SRC					58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define CSI3_CLK_SRC					59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define FD_CORE_CLK_SRC					60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define MMSS_CXO_CLK					61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define MMSS_SLEEPCLK_CLK				62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define MMSS_MMAGIC_AHB_CLK				63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define MMSS_MMAGIC_CFG_AHB_CLK				64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define MMSS_MISC_AHB_CLK				65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define MMSS_MISC_CXO_CLK				66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define MMSS_BTO_AHB_CLK				67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define MMSS_MMAGIC_AXI_CLK				68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define MMSS_S0_AXI_CLK					69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define MMSS_MMAGIC_MAXI_CLK				70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define DSA_CORE_CLK					71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define DSA_NOC_CFG_AHB_CLK				72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define MMAGIC_CAMSS_AXI_CLK				73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define MMAGIC_CAMSS_NOC_CFG_AHB_CLK			74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define THROTTLE_CAMSS_CXO_CLK				75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define THROTTLE_CAMSS_AHB_CLK				76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define THROTTLE_CAMSS_AXI_CLK				77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define SMMU_VFE_AHB_CLK				78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define SMMU_VFE_AXI_CLK				79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define SMMU_CPP_AHB_CLK				80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define SMMU_CPP_AXI_CLK				81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define SMMU_JPEG_AHB_CLK				82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define SMMU_JPEG_AXI_CLK				83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define MMAGIC_MDSS_AXI_CLK				84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define MMAGIC_MDSS_NOC_CFG_AHB_CLK			85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define THROTTLE_MDSS_CXO_CLK				86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define THROTTLE_MDSS_AHB_CLK				87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define THROTTLE_MDSS_AXI_CLK				88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define SMMU_ROT_AHB_CLK				89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define SMMU_ROT_AXI_CLK				90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SMMU_MDP_AHB_CLK				91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SMMU_MDP_AXI_CLK				92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define MMAGIC_VIDEO_AXI_CLK				93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define MMAGIC_VIDEO_NOC_CFG_AHB_CLK			94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define THROTTLE_VIDEO_CXO_CLK				95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define THROTTLE_VIDEO_AHB_CLK				96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define THROTTLE_VIDEO_AXI_CLK				97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SMMU_VIDEO_AHB_CLK				98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define SMMU_VIDEO_AXI_CLK				99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define MMAGIC_BIMC_AXI_CLK				100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define MMAGIC_BIMC_NOC_CFG_AHB_CLK			101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define GPU_GX_GFX3D_CLK				102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define GPU_GX_RBBMTIMER_CLK				103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define GPU_AHB_CLK					104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define GPU_AON_ISENSE_CLK				105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define VMEM_MAXI_CLK					106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define VMEM_AHB_CLK					107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define MMSS_RBCPR_CLK					108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define MMSS_RBCPR_AHB_CLK				109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define VIDEO_CORE_CLK					110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define VIDEO_AXI_CLK					111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define VIDEO_MAXI_CLK					112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define VIDEO_AHB_CLK					113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define VIDEO_SUBCORE0_CLK				114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define VIDEO_SUBCORE1_CLK				115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define MDSS_AHB_CLK					116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define MDSS_HDMI_AHB_CLK				117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define MDSS_AXI_CLK					118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define MDSS_PCLK0_CLK					119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define MDSS_PCLK1_CLK					120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define MDSS_MDP_CLK					121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define MDSS_EXTPCLK_CLK				122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define MDSS_VSYNC_CLK					123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define MDSS_HDMI_CLK					124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define MDSS_BYTE0_CLK					125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define MDSS_BYTE1_CLK					126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define MDSS_ESC0_CLK					127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define MDSS_ESC1_CLK					128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define CAMSS_TOP_AHB_CLK				129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define CAMSS_AHB_CLK					130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define CAMSS_MICRO_AHB_CLK				131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define CAMSS_GP0_CLK					132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define CAMSS_GP1_CLK					133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define CAMSS_MCLK0_CLK					134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define CAMSS_MCLK1_CLK					135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define CAMSS_MCLK2_CLK					136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define CAMSS_MCLK3_CLK					137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define CAMSS_CCI_CLK					138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define CAMSS_CCI_AHB_CLK				139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define CAMSS_CSI0PHYTIMER_CLK				140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define CAMSS_CSI1PHYTIMER_CLK				141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define CAMSS_CSI2PHYTIMER_CLK				142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define CAMSS_CSIPHY0_3P_CLK				143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define CAMSS_CSIPHY1_3P_CLK				144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define CAMSS_CSIPHY2_3P_CLK				145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define CAMSS_JPEG0_CLK					146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define CAMSS_JPEG2_CLK					147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define CAMSS_JPEG_DMA_CLK				148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define CAMSS_JPEG_AHB_CLK				149
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define CAMSS_JPEG_AXI_CLK				150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define CAMSS_VFE_AHB_CLK				151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define CAMSS_VFE_AXI_CLK				152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define CAMSS_VFE0_CLK					153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define CAMSS_VFE0_STREAM_CLK				154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define CAMSS_VFE0_AHB_CLK				155
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define CAMSS_VFE1_CLK					156
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define CAMSS_VFE1_STREAM_CLK				157
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define CAMSS_VFE1_AHB_CLK				158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define CAMSS_CSI_VFE0_CLK				159
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define CAMSS_CSI_VFE1_CLK				160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define CAMSS_CPP_VBIF_AHB_CLK				161
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define CAMSS_CPP_AXI_CLK				162
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define CAMSS_CPP_CLK					163
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define CAMSS_CPP_AHB_CLK				164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define CAMSS_CSI0_CLK					165
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define CAMSS_CSI0_AHB_CLK				166
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define CAMSS_CSI0PHY_CLK				167
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define CAMSS_CSI0RDI_CLK				168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define CAMSS_CSI0PIX_CLK				169
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define CAMSS_CSI1_CLK					170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define CAMSS_CSI1_AHB_CLK				171
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define CAMSS_CSI1PHY_CLK				172
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define CAMSS_CSI1RDI_CLK				173
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define CAMSS_CSI1PIX_CLK				174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define CAMSS_CSI2_CLK					175
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define CAMSS_CSI2_AHB_CLK				176
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define CAMSS_CSI2PHY_CLK				177
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define CAMSS_CSI2RDI_CLK				178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define CAMSS_CSI2PIX_CLK				179
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define CAMSS_CSI3_CLK					180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define CAMSS_CSI3_AHB_CLK				181
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define CAMSS_CSI3PHY_CLK				182
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define CAMSS_CSI3RDI_CLK				183
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define CAMSS_CSI3PIX_CLK				184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define CAMSS_ISPIF_AHB_CLK				185
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define FD_CORE_CLK					186
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define FD_CORE_UAR_CLK					187
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define FD_AHB_CLK					188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define MMSS_SPDM_CSI0_CLK				189
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define MMSS_SPDM_JPEG_DMA_CLK				190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define MMSS_SPDM_CPP_CLK				191
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define MMSS_SPDM_PCLK0_CLK				192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define MMSS_SPDM_AHB_CLK				193
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define MMSS_SPDM_GFX3D_CLK				194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define MMSS_SPDM_PCLK1_CLK				195
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define MMSS_SPDM_JPEG2_CLK				196
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define MMSS_SPDM_DEBUG_CLK				197
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define MMSS_SPDM_VFE1_CLK				198
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define MMSS_SPDM_VFE0_CLK				199
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define MMSS_SPDM_VIDEO_CORE_CLK			200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define MMSS_SPDM_AXI_CLK				201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define MMSS_SPDM_MDP_CLK				202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define MMSS_SPDM_JPEG0_CLK				203
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define MMSS_SPDM_RM_AXI_CLK				204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define MMSS_SPDM_RM_MAXI_CLK				205
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define MMAGICAHB_BCR					0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define MMAGIC_CFG_BCR					1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define MISC_BCR					2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define BTO_BCR						3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define MMAGICAXI_BCR					4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define MMAGICMAXI_BCR					5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define DSA_BCR						6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define MMAGIC_CAMSS_BCR				7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define THROTTLE_CAMSS_BCR				8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define SMMU_VFE_BCR					9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define SMMU_CPP_BCR					10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define SMMU_JPEG_BCR					11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define MMAGIC_MDSS_BCR					12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define THROTTLE_MDSS_BCR				13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define SMMU_ROT_BCR					14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define SMMU_MDP_BCR					15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define MMAGIC_VIDEO_BCR				16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define THROTTLE_VIDEO_BCR				17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define SMMU_VIDEO_BCR					18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define MMAGIC_BIMC_BCR					19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define GPU_GX_BCR					20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define GPU_BCR						21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define GPU_AON_BCR					22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define VMEM_BCR					23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define MMSS_RBCPR_BCR					24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define VIDEO_BCR					25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define MDSS_BCR					26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define CAMSS_TOP_BCR					27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define CAMSS_AHB_BCR					28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define CAMSS_MICRO_BCR					29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define CAMSS_CCI_BCR					30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define CAMSS_PHY0_BCR					31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define CAMSS_PHY1_BCR					32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define CAMSS_PHY2_BCR					33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define CAMSS_CSIPHY0_3P_BCR				34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define CAMSS_CSIPHY1_3P_BCR				35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define CAMSS_CSIPHY2_3P_BCR				36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define CAMSS_JPEG_BCR					37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define CAMSS_VFE_BCR					38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define CAMSS_VFE0_BCR					39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define CAMSS_VFE1_BCR					40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define CAMSS_CSI_VFE0_BCR				41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define CAMSS_CSI_VFE1_BCR				42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define CAMSS_CPP_TOP_BCR				43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define CAMSS_CPP_BCR					44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define CAMSS_CSI0_BCR					45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define CAMSS_CSI0RDI_BCR				46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define CAMSS_CSI0PIX_BCR				47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define CAMSS_CSI1_BCR					48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define CAMSS_CSI1RDI_BCR				49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define CAMSS_CSI1PIX_BCR				50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define CAMSS_CSI2_BCR					51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define CAMSS_CSI2RDI_BCR				52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define CAMSS_CSI2PIX_BCR				53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define CAMSS_CSI3_BCR					54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define CAMSS_CSI3RDI_BCR				55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define CAMSS_CSI3PIX_BCR				56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define CAMSS_ISPIF_BCR					57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define FD_BCR						58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define MMSS_SPDM_RM_BCR				59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /* Indexes for GDSCs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define MMAGIC_VIDEO_GDSC	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define MMAGIC_MDSS_GDSC	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define MMAGIC_CAMSS_GDSC	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define GPU_GDSC		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define VENUS_GDSC		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define VENUS_CORE0_GDSC	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define VENUS_CORE1_GDSC	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define CAMSS_GDSC		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define VFE0_GDSC		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define VFE1_GDSC		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define JPEG_GDSC		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define CPP_GDSC		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define FD_GDSC			12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define MDSS_GDSC		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define GPU_GX_GDSC		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define MMAGIC_BIMC_GDSC	15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #endif