^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2013, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef _DT_BINDINGS_CLK_MSM_MMCC_8960_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define _DT_BINDINGS_CLK_MSM_MMCC_8960_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define MMSS_AHB_SRC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define FAB_AHB_CLK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define APU_AHB_CLK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define TV_ENC_AHB_CLK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define AMP_AHB_CLK 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define DSI2_S_AHB_CLK 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define JPEGD_AHB_CLK 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define GFX2D0_AHB_CLK 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define DSI_S_AHB_CLK 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define DSI2_M_AHB_CLK 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define VPE_AHB_CLK 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SMMU_AHB_CLK 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define HDMI_M_AHB_CLK 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define VFE_AHB_CLK 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define ROT_AHB_CLK 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define VCODEC_AHB_CLK 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MDP_AHB_CLK 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DSI_M_AHB_CLK 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CSI_AHB_CLK 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MMSS_IMEM_AHB_CLK 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define IJPEG_AHB_CLK 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define HDMI_S_AHB_CLK 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define GFX3D_AHB_CLK 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define GFX2D1_AHB_CLK 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MMSS_FPB_CLK 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MMSS_AXI_SRC 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MMSS_FAB_CORE 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define FAB_MSP_AXI_CLK 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define JPEGD_AXI_CLK 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define GMEM_AXI_CLK 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MDP_AXI_CLK 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MMSS_IMEM_AXI_CLK 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define IJPEG_AXI_CLK 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define GFX3D_AXI_CLK 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define VCODEC_AXI_CLK 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define VFE_AXI_CLK 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define VPE_AXI_CLK 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define ROT_AXI_CLK 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define VCODEC_AXI_A_CLK 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define VCODEC_AXI_B_CLK 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MM_AXI_S3_FCLK 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MM_AXI_S2_FCLK 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MM_AXI_S1_FCLK 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MM_AXI_S0_FCLK 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MM_AXI_S2_CLK 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MM_AXI_S1_CLK 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MM_AXI_S0_CLK 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CSI0_SRC 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CSI0_CLK 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CSI0_PHY_CLK 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CSI1_SRC 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CSI1_CLK 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CSI1_PHY_CLK 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CSI2_SRC 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CSI2_CLK 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CSI2_PHY_CLK 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define DSI_SRC 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define DSI_CLK 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define CSI_PIX_CLK 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define CSI_RDI_CLK 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define MDP_VSYNC_CLK 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define HDMI_DIV_CLK 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define HDMI_APP_CLK 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define CSI_PIX1_CLK 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define CSI_RDI2_CLK 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define CSI_RDI1_CLK 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define GFX2D0_SRC 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define GFX2D0_CLK 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define GFX2D1_SRC 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define GFX2D1_CLK 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define GFX3D_SRC 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define GFX3D_CLK 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define IJPEG_SRC 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define IJPEG_CLK 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define JPEGD_SRC 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define JPEGD_CLK 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define MDP_SRC 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define MDP_CLK 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define MDP_LUT_CLK 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define DSI2_PIXEL_SRC 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define DSI2_PIXEL_CLK 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define DSI2_SRC 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define DSI2_CLK 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define DSI1_BYTE_SRC 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define DSI1_BYTE_CLK 84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define DSI2_BYTE_SRC 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define DSI2_BYTE_CLK 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define DSI1_ESC_SRC 87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define DSI1_ESC_CLK 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define DSI2_ESC_SRC 89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define DSI2_ESC_CLK 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define ROT_SRC 91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define ROT_CLK 92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define TV_ENC_CLK 93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define TV_DAC_CLK 94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define HDMI_TV_CLK 95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define MDP_TV_CLK 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define TV_SRC 97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define VCODEC_SRC 98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define VCODEC_CLK 99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define VFE_SRC 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define VFE_CLK 101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define VFE_CSI_CLK 102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define VPE_SRC 103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define VPE_CLK 104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define DSI_PIXEL_SRC 105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define DSI_PIXEL_CLK 106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define CAMCLK0_SRC 107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define CAMCLK0_CLK 108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define CAMCLK1_SRC 109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define CAMCLK1_CLK 110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define CAMCLK2_SRC 111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define CAMCLK2_CLK 112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define CSIPHYTIMER_SRC 113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define CSIPHY2_TIMER_CLK 114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define CSIPHY1_TIMER_CLK 115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define CSIPHY0_TIMER_CLK 116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define PLL1 117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define PLL2 118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define RGB_TV_CLK 119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define NPL_TV_CLK 120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define VCAP_AHB_CLK 121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define VCAP_AXI_CLK 122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define VCAP_SRC 123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define VCAP_CLK 124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define VCAP_NPL_CLK 125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define PLL15 126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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