^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2014, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef _DT_BINDINGS_CLK_APQ_MMCC_8084_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define _DT_BINDINGS_CLK_APQ_MMCC_8084_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define MMSS_AHB_CLK_SRC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define MMSS_AXI_CLK_SRC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define MMPLL0 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define MMPLL0_VOTE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define MMPLL1 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define MMPLL1_VOTE 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define MMPLL2 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define MMPLL3 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define MMPLL4 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CSI0_CLK_SRC 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CSI1_CLK_SRC 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CSI2_CLK_SRC 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CSI3_CLK_SRC 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define VCODEC0_CLK_SRC 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define VFE0_CLK_SRC 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define VFE1_CLK_SRC 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MDP_CLK_SRC 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PCLK0_CLK_SRC 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PCLK1_CLK_SRC 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define OCMEMNOC_CLK_SRC 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define GFX3D_CLK_SRC 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define JPEG0_CLK_SRC 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define JPEG1_CLK_SRC 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define JPEG2_CLK_SRC 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define EDPPIXEL_CLK_SRC 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define EXTPCLK_CLK_SRC 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define VP_CLK_SRC 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CCI_CLK_SRC 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CAMSS_GP0_CLK_SRC 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CAMSS_GP1_CLK_SRC 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MCLK0_CLK_SRC 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MCLK1_CLK_SRC 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MCLK2_CLK_SRC 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MCLK3_CLK_SRC 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CSI0PHYTIMER_CLK_SRC 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CSI1PHYTIMER_CLK_SRC 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CSI2PHYTIMER_CLK_SRC 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CPP_CLK_SRC 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define BYTE0_CLK_SRC 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define BYTE1_CLK_SRC 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define EDPAUX_CLK_SRC 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define EDPLINK_CLK_SRC 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define ESC0_CLK_SRC 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define ESC1_CLK_SRC 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define HDMI_CLK_SRC 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define VSYNC_CLK_SRC 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MMSS_RBCPR_CLK_SRC 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define RBBMTIMER_CLK_SRC 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MAPLE_CLK_SRC 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define VDP_CLK_SRC 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define VPU_BUS_CLK_SRC 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MMSS_CXO_CLK 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MMSS_SLEEPCLK_CLK 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define AVSYNC_AHB_CLK 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define AVSYNC_EDPPIXEL_CLK 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define AVSYNC_EXTPCLK_CLK 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define AVSYNC_PCLK0_CLK 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define AVSYNC_PCLK1_CLK 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define AVSYNC_VP_CLK 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define CAMSS_AHB_CLK 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define CAMSS_CCI_CCI_AHB_CLK 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define CAMSS_CCI_CCI_CLK 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define CAMSS_CSI0_AHB_CLK 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define CAMSS_CSI0_CLK 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define CAMSS_CSI0PHY_CLK 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define CAMSS_CSI0PIX_CLK 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define CAMSS_CSI0RDI_CLK 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define CAMSS_CSI1_AHB_CLK 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define CAMSS_CSI1_CLK 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define CAMSS_CSI1PHY_CLK 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define CAMSS_CSI1PIX_CLK 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define CAMSS_CSI1RDI_CLK 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define CAMSS_CSI2_AHB_CLK 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define CAMSS_CSI2_CLK 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define CAMSS_CSI2PHY_CLK 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define CAMSS_CSI2PIX_CLK 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define CAMSS_CSI2RDI_CLK 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define CAMSS_CSI3_AHB_CLK 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define CAMSS_CSI3_CLK 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define CAMSS_CSI3PHY_CLK 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define CAMSS_CSI3PIX_CLK 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define CAMSS_CSI3RDI_CLK 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define CAMSS_CSI_VFE0_CLK 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define CAMSS_CSI_VFE1_CLK 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define CAMSS_GP0_CLK 84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define CAMSS_GP1_CLK 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define CAMSS_ISPIF_AHB_CLK 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define CAMSS_JPEG_JPEG0_CLK 87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define CAMSS_JPEG_JPEG1_CLK 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define CAMSS_JPEG_JPEG2_CLK 89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define CAMSS_JPEG_JPEG_AHB_CLK 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define CAMSS_JPEG_JPEG_AXI_CLK 91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define CAMSS_MCLK0_CLK 92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define CAMSS_MCLK1_CLK 93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define CAMSS_MCLK2_CLK 94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define CAMSS_MCLK3_CLK 95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define CAMSS_MICRO_AHB_CLK 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define CAMSS_PHY0_CSI0PHYTIMER_CLK 97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define CAMSS_PHY1_CSI1PHYTIMER_CLK 98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define CAMSS_PHY2_CSI2PHYTIMER_CLK 99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define CAMSS_TOP_AHB_CLK 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define CAMSS_VFE_CPP_AHB_CLK 101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define CAMSS_VFE_CPP_CLK 102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define CAMSS_VFE_VFE0_CLK 103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define CAMSS_VFE_VFE1_CLK 104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define CAMSS_VFE_VFE_AHB_CLK 105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define CAMSS_VFE_VFE_AXI_CLK 106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define MDSS_AHB_CLK 107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define MDSS_AXI_CLK 108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define MDSS_BYTE0_CLK 109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define MDSS_BYTE1_CLK 110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define MDSS_EDPAUX_CLK 111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define MDSS_EDPLINK_CLK 112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define MDSS_EDPPIXEL_CLK 113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define MDSS_ESC0_CLK 114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define MDSS_ESC1_CLK 115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define MDSS_EXTPCLK_CLK 116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define MDSS_HDMI_AHB_CLK 117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define MDSS_HDMI_CLK 118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define MDSS_MDP_CLK 119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define MDSS_MDP_LUT_CLK 120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define MDSS_PCLK0_CLK 121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define MDSS_PCLK1_CLK 122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define MDSS_VSYNC_CLK 123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define MMSS_RBCPR_AHB_CLK 124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define MMSS_RBCPR_CLK 125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define MMSS_SPDM_AHB_CLK 126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define MMSS_SPDM_AXI_CLK 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define MMSS_SPDM_CSI0_CLK 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define MMSS_SPDM_GFX3D_CLK 129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define MMSS_SPDM_JPEG0_CLK 130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define MMSS_SPDM_JPEG1_CLK 131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define MMSS_SPDM_JPEG2_CLK 132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define MMSS_SPDM_MDP_CLK 133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define MMSS_SPDM_PCLK0_CLK 134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define MMSS_SPDM_PCLK1_CLK 135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define MMSS_SPDM_VCODEC0_CLK 136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define MMSS_SPDM_VFE0_CLK 137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define MMSS_SPDM_VFE1_CLK 138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define MMSS_SPDM_RM_AXI_CLK 139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define MMSS_SPDM_RM_OCMEMNOC_CLK 140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define MMSS_MISC_AHB_CLK 141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define MMSS_MMSSNOC_AHB_CLK 142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define MMSS_MMSSNOC_BTO_AHB_CLK 143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define MMSS_MMSSNOC_AXI_CLK 144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define MMSS_S0_AXI_CLK 145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define OCMEMCX_AHB_CLK 146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define OCMEMCX_OCMEMNOC_CLK 147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define OXILI_OCMEMGX_CLK 148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define OXILI_GFX3D_CLK 149
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define OXILI_RBBMTIMER_CLK 150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define OXILICX_AHB_CLK 151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define VENUS0_AHB_CLK 152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define VENUS0_AXI_CLK 153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define VENUS0_CORE0_VCODEC_CLK 154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define VENUS0_CORE1_VCODEC_CLK 155
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define VENUS0_OCMEMNOC_CLK 156
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define VENUS0_VCODEC0_CLK 157
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define VPU_AHB_CLK 158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define VPU_AXI_CLK 159
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define VPU_BUS_CLK 160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define VPU_CXO_CLK 161
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define VPU_MAPLE_CLK 162
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define VPU_SLEEP_CLK 163
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define VPU_VDP_CLK 164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* GDSCs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define VENUS0_GDSC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define VENUS0_CORE0_GDSC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define VENUS0_CORE1_GDSC 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define MDSS_GDSC 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define CAMSS_JPEG_GDSC 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define CAMSS_VFE_GDSC 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define OXILI_GDSC 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define OXILICX_GDSC 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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