Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (c) 2014, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * Copyright (c) BayLibre, SAS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Author : Neil Armstrong <narmstrong@baylibre.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #ifndef _DT_BINDINGS_CLK_LCC_MDM9615_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define _DT_BINDINGS_CLK_LCC_MDM9615_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define PLL4				0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define MI2S_OSR_SRC			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define MI2S_OSR_CLK			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define MI2S_DIV_CLK			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define MI2S_BIT_DIV_CLK		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define MI2S_BIT_CLK			5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define PCM_SRC				6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PCM_CLK_OUT			7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PCM_CLK				8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SLIMBUS_SRC			9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define AUDIO_SLIMBUS_CLK		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SPS_SLIMBUS_CLK			11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CODEC_I2S_MIC_OSR_SRC		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CODEC_I2S_MIC_OSR_CLK		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CODEC_I2S_MIC_DIV_CLK		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CODEC_I2S_MIC_BIT_DIV_CLK	15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CODEC_I2S_MIC_BIT_CLK		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SPARE_I2S_MIC_OSR_SRC		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SPARE_I2S_MIC_OSR_CLK		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SPARE_I2S_MIC_DIV_CLK		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SPARE_I2S_MIC_BIT_DIV_CLK	20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SPARE_I2S_MIC_BIT_CLK		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CODEC_I2S_SPKR_OSR_SRC		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CODEC_I2S_SPKR_OSR_CLK		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CODEC_I2S_SPKR_DIV_CLK		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CODEC_I2S_SPKR_BIT_DIV_CLK	25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CODEC_I2S_SPKR_BIT_CLK		26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SPARE_I2S_SPKR_OSR_SRC		27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SPARE_I2S_SPKR_OSR_CLK		28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SPARE_I2S_SPKR_DIV_CLK		29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SPARE_I2S_SPKR_BIT_DIV_CLK	30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SPARE_I2S_SPKR_BIT_CLK		31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #endif