Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8250_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8250_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) /* GPU_CC clock registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define GPU_CC_AHB_CLK				0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define GPU_CC_CRC_AHB_CLK			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define GPU_CC_CX_APB_CLK			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define GPU_CC_CX_GMU_CLK			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define GPU_CC_CX_SNOC_DVM_CLK			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define GPU_CC_CXO_AON_CLK			5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define GPU_CC_CXO_CLK				6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define GPU_CC_GMU_CLK_SRC			7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define GPU_CC_GX_GMU_CLK			8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define GPU_CC_PLL1				9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* GPU_CC Resets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define GPUCC_GPU_CC_ACD_BCR			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define GPUCC_GPU_CC_CX_BCR			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define GPUCC_GPU_CC_GFX3D_AON_BCR		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define GPUCC_GPU_CC_GMU_BCR			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define GPUCC_GPU_CC_GX_BCR			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define GPUCC_GPU_CC_XO_BCR			5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* GPU_CC GDSCRs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define GPU_CX_GDSC				0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define GPU_GX_GDSC				1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #endif