Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2019, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM8150_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #define _DT_BINDINGS_CLK_QCOM_GCC_SM8150_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) /* GCC clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #define GCC_AGGRE_NOC_PCIE_TBU_CLK				0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define GCC_AGGRE_UFS_CARD_AXI_CLK				1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define GCC_AGGRE_UFS_PHY_AXI_CLK				3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define GCC_AGGRE_USB3_PRIM_AXI_CLK				5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define GCC_AGGRE_USB3_SEC_AXI_CLK				6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define GCC_BOOT_ROM_AHB_CLK					7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define GCC_CAMERA_AHB_CLK					8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define GCC_CAMERA_HF_AXI_CLK					9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define GCC_CAMERA_SF_AXI_CLK					10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define GCC_CAMERA_XO_CLK					11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define GCC_CFG_NOC_USB3_PRIM_AXI_CLK				12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define GCC_CFG_NOC_USB3_SEC_AXI_CLK				13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define GCC_CPUSS_AHB_CLK					14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define GCC_CPUSS_AHB_CLK_SRC					15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define GCC_CPUSS_DVM_BUS_CLK					16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define GCC_CPUSS_GNOC_CLK					17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define GCC_CPUSS_RBCPR_CLK					18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define GCC_DDRSS_GPU_AXI_CLK					19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define GCC_DISP_AHB_CLK					20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define GCC_DISP_HF_AXI_CLK					21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define GCC_DISP_SF_AXI_CLK					22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define GCC_DISP_XO_CLK						23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define GCC_EMAC_AXI_CLK					24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define GCC_EMAC_PTP_CLK					25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define GCC_EMAC_PTP_CLK_SRC					26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define GCC_EMAC_RGMII_CLK					27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define GCC_EMAC_RGMII_CLK_SRC					28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define GCC_EMAC_SLV_AHB_CLK					29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define GCC_GP1_CLK						30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define GCC_GP1_CLK_SRC						31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define GCC_GP2_CLK						32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define GCC_GP2_CLK_SRC						33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define GCC_GP3_CLK						34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define GCC_GP3_CLK_SRC						35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define GCC_GPU_CFG_AHB_CLK					36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define GCC_GPU_GPLL0_CLK_SRC					37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define GCC_GPU_GPLL0_DIV_CLK_SRC				38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define GCC_GPU_IREF_CLK					39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define GCC_GPU_MEMNOC_GFX_CLK					40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define GCC_GPU_SNOC_DVM_GFX_CLK				41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define GCC_NPU_AT_CLK						42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define GCC_NPU_AXI_CLK						43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define GCC_NPU_CFG_AHB_CLK					44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define GCC_NPU_GPLL0_CLK_SRC					45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define GCC_NPU_GPLL0_DIV_CLK_SRC				46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define GCC_NPU_TRIG_CLK					47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define GCC_PCIE0_PHY_REFGEN_CLK				48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define GCC_PCIE1_PHY_REFGEN_CLK				49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define GCC_PCIE_0_AUX_CLK					50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define GCC_PCIE_0_AUX_CLK_SRC					51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define GCC_PCIE_0_CFG_AHB_CLK					52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define GCC_PCIE_0_CLKREF_CLK					53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define GCC_PCIE_0_MSTR_AXI_CLK					54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define GCC_PCIE_0_PIPE_CLK					55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define GCC_PCIE_0_SLV_AXI_CLK					56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define GCC_PCIE_0_SLV_Q2A_AXI_CLK				57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define GCC_PCIE_1_AUX_CLK					58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define GCC_PCIE_1_AUX_CLK_SRC					59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define GCC_PCIE_1_CFG_AHB_CLK					60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define GCC_PCIE_1_CLKREF_CLK					61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define GCC_PCIE_1_MSTR_AXI_CLK					62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define GCC_PCIE_1_PIPE_CLK					63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define GCC_PCIE_1_SLV_AXI_CLK					64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define GCC_PCIE_1_SLV_Q2A_AXI_CLK				65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define GCC_PCIE_PHY_AUX_CLK					66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define GCC_PCIE_PHY_REFGEN_CLK_SRC				67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define GCC_PDM2_CLK						68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define GCC_PDM2_CLK_SRC					69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define GCC_PDM_AHB_CLK						70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define GCC_PDM_XO4_CLK						71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define GCC_PRNG_AHB_CLK					72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define GCC_QMIP_CAMERA_NRT_AHB_CLK				73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define GCC_QMIP_CAMERA_RT_AHB_CLK				74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define GCC_QMIP_DISP_AHB_CLK					75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define GCC_QMIP_VIDEO_CVP_AHB_CLK				76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define GCC_QMIP_VIDEO_VCODEC_AHB_CLK				77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define GCC_QSPI_CNOC_PERIPH_AHB_CLK				78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define GCC_QSPI_CORE_CLK					79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define GCC_QSPI_CORE_CLK_SRC					80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define GCC_QUPV3_WRAP0_S0_CLK					81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define GCC_QUPV3_WRAP0_S0_CLK_SRC				82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define GCC_QUPV3_WRAP0_S1_CLK					83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define GCC_QUPV3_WRAP0_S1_CLK_SRC				84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define GCC_QUPV3_WRAP0_S2_CLK					85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define GCC_QUPV3_WRAP0_S2_CLK_SRC				86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define GCC_QUPV3_WRAP0_S3_CLK					87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define GCC_QUPV3_WRAP0_S3_CLK_SRC				88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define GCC_QUPV3_WRAP0_S4_CLK					89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define GCC_QUPV3_WRAP0_S4_CLK_SRC				90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define GCC_QUPV3_WRAP0_S5_CLK					91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define GCC_QUPV3_WRAP0_S5_CLK_SRC				92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define GCC_QUPV3_WRAP0_S6_CLK					93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define GCC_QUPV3_WRAP0_S6_CLK_SRC				94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define GCC_QUPV3_WRAP0_S7_CLK					95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define GCC_QUPV3_WRAP0_S7_CLK_SRC				96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define GCC_QUPV3_WRAP1_S0_CLK					97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define GCC_QUPV3_WRAP1_S0_CLK_SRC				98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define GCC_QUPV3_WRAP1_S1_CLK					99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define GCC_QUPV3_WRAP1_S1_CLK_SRC				100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define GCC_QUPV3_WRAP1_S2_CLK					101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define GCC_QUPV3_WRAP1_S2_CLK_SRC				102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define GCC_QUPV3_WRAP1_S3_CLK					103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define GCC_QUPV3_WRAP1_S3_CLK_SRC				104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define GCC_QUPV3_WRAP1_S4_CLK					105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define GCC_QUPV3_WRAP1_S4_CLK_SRC				106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define GCC_QUPV3_WRAP1_S5_CLK					107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define GCC_QUPV3_WRAP1_S5_CLK_SRC				108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define GCC_QUPV3_WRAP2_S0_CLK					109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define GCC_QUPV3_WRAP2_S0_CLK_SRC				110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define GCC_QUPV3_WRAP2_S1_CLK					111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define GCC_QUPV3_WRAP2_S1_CLK_SRC				112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define GCC_QUPV3_WRAP2_S2_CLK					113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define GCC_QUPV3_WRAP2_S2_CLK_SRC				114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define GCC_QUPV3_WRAP2_S3_CLK					115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define GCC_QUPV3_WRAP2_S3_CLK_SRC				116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define GCC_QUPV3_WRAP2_S4_CLK					117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define GCC_QUPV3_WRAP2_S4_CLK_SRC				118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define GCC_QUPV3_WRAP2_S5_CLK					119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define GCC_QUPV3_WRAP2_S5_CLK_SRC				120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define GCC_QUPV3_WRAP_0_M_AHB_CLK				121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define GCC_QUPV3_WRAP_0_S_AHB_CLK				122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define GCC_QUPV3_WRAP_1_M_AHB_CLK				123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define GCC_QUPV3_WRAP_1_S_AHB_CLK				124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define GCC_QUPV3_WRAP_2_M_AHB_CLK				125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define GCC_QUPV3_WRAP_2_S_AHB_CLK				126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define GCC_SDCC2_AHB_CLK					127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define GCC_SDCC2_APPS_CLK					128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define GCC_SDCC2_APPS_CLK_SRC					129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define GCC_SDCC4_AHB_CLK					130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define GCC_SDCC4_APPS_CLK					131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define GCC_SDCC4_APPS_CLK_SRC					132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define GCC_SYS_NOC_CPUSS_AHB_CLK				133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define GCC_TSIF_AHB_CLK					134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define GCC_TSIF_INACTIVITY_TIMERS_CLK				135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define GCC_TSIF_REF_CLK					136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define GCC_TSIF_REF_CLK_SRC					137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define GCC_UFS_CARD_AHB_CLK					138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define GCC_UFS_CARD_AXI_CLK					139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define GCC_UFS_CARD_AXI_CLK_SRC				140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define GCC_UFS_CARD_AXI_HW_CTL_CLK				141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define GCC_UFS_CARD_CLKREF_CLK					142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define GCC_UFS_CARD_ICE_CORE_CLK				143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define GCC_UFS_CARD_ICE_CORE_CLK_SRC				144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK			145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define GCC_UFS_CARD_PHY_AUX_CLK				146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define GCC_UFS_CARD_PHY_AUX_CLK_SRC				147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK				148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define GCC_UFS_CARD_RX_SYMBOL_0_CLK				149
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define GCC_UFS_CARD_RX_SYMBOL_1_CLK				150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define GCC_UFS_CARD_TX_SYMBOL_0_CLK				151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define GCC_UFS_CARD_UNIPRO_CORE_CLK				152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC			153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK			154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define GCC_UFS_MEM_CLKREF_CLK					155
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define GCC_UFS_PHY_AHB_CLK					156
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define GCC_UFS_PHY_AXI_CLK					157
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define GCC_UFS_PHY_AXI_CLK_SRC					158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define GCC_UFS_PHY_AXI_HW_CTL_CLK				159
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define GCC_UFS_PHY_ICE_CORE_CLK				160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define GCC_UFS_PHY_ICE_CORE_CLK_SRC				161
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK				162
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define GCC_UFS_PHY_PHY_AUX_CLK					163
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define GCC_UFS_PHY_PHY_AUX_CLK_SRC				164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK				165
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define GCC_UFS_PHY_RX_SYMBOL_0_CLK				166
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define GCC_UFS_PHY_RX_SYMBOL_1_CLK				167
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define GCC_UFS_PHY_TX_SYMBOL_0_CLK				168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define GCC_UFS_PHY_UNIPRO_CORE_CLK				169
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC				170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK			171
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define GCC_USB30_PRIM_MASTER_CLK				172
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define GCC_USB30_PRIM_MASTER_CLK_SRC				173
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define GCC_USB30_PRIM_MOCK_UTMI_CLK				174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC			175
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define GCC_USB30_PRIM_SLEEP_CLK				176
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define GCC_USB30_SEC_MASTER_CLK				177
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define GCC_USB30_SEC_MASTER_CLK_SRC				178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define GCC_USB30_SEC_MOCK_UTMI_CLK				179
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC				180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define GCC_USB30_SEC_SLEEP_CLK					181
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define GCC_USB3_PRIM_CLKREF_CLK				182
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define GCC_USB3_PRIM_PHY_AUX_CLK				183
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define GCC_USB3_PRIM_PHY_AUX_CLK_SRC				184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define GCC_USB3_PRIM_PHY_COM_AUX_CLK				185
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define GCC_USB3_PRIM_PHY_PIPE_CLK				186
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define GCC_USB3_SEC_CLKREF_CLK					187
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define GCC_USB3_SEC_PHY_AUX_CLK				188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define GCC_USB3_SEC_PHY_AUX_CLK_SRC				189
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define GCC_USB3_SEC_PHY_COM_AUX_CLK				190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define GCC_USB3_SEC_PHY_PIPE_CLK				191
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define GCC_VIDEO_AHB_CLK					192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define GCC_VIDEO_AXI0_CLK					193
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define GCC_VIDEO_AXI1_CLK					194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define GCC_VIDEO_AXIC_CLK					195
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define GCC_VIDEO_XO_CLK					196
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define GPLL0							197
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define GPLL0_OUT_EVEN						198
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define GPLL7							199
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define GPLL9							200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* Reset clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define GCC_EMAC_BCR						0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define GCC_GPU_BCR						1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define GCC_MMSS_BCR						2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define GCC_NPU_BCR						3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define GCC_PCIE_0_BCR						4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define GCC_PCIE_0_PHY_BCR					5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define GCC_PCIE_1_BCR						6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define GCC_PCIE_1_PHY_BCR					7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define GCC_PCIE_PHY_BCR					8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define GCC_PDM_BCR						9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define GCC_PRNG_BCR						10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define GCC_QSPI_BCR						11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define GCC_QUPV3_WRAPPER_0_BCR					12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define GCC_QUPV3_WRAPPER_1_BCR					13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define GCC_QUPV3_WRAPPER_2_BCR					14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define GCC_QUSB2PHY_PRIM_BCR					15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define GCC_QUSB2PHY_SEC_BCR					16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define GCC_USB3_PHY_PRIM_BCR					17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define GCC_USB3_DP_PHY_PRIM_BCR				18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define GCC_USB3_PHY_SEC_BCR					19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define GCC_USB3PHY_PHY_SEC_BCR					20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define GCC_SDCC2_BCR						21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define GCC_SDCC4_BCR						22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define GCC_TSIF_BCR						23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define GCC_UFS_CARD_BCR					24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define GCC_UFS_PHY_BCR						25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define GCC_USB30_PRIM_BCR					26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define GCC_USB30_SEC_BCR					27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define GCC_USB_PHY_CFG_AHB2PHY_BCR				28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* GCC GDSCRs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define USB30_PRIM_GDSC                     4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define USB30_SEC_GDSC						5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #endif