^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2018, Craig Tatlor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef _DT_BINDINGS_CLK_MSM_GCC_660_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define _DT_BINDINGS_CLK_MSM_GCC_660_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define BLSP1_QUP1_I2C_APPS_CLK_SRC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define BLSP1_QUP1_SPI_APPS_CLK_SRC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define BLSP1_QUP2_I2C_APPS_CLK_SRC 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define BLSP1_QUP2_SPI_APPS_CLK_SRC 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define BLSP1_QUP3_I2C_APPS_CLK_SRC 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define BLSP1_QUP3_SPI_APPS_CLK_SRC 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define BLSP1_QUP4_I2C_APPS_CLK_SRC 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define BLSP1_QUP4_SPI_APPS_CLK_SRC 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define BLSP1_UART1_APPS_CLK_SRC 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define BLSP1_UART2_APPS_CLK_SRC 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define BLSP2_QUP1_I2C_APPS_CLK_SRC 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define BLSP2_QUP1_SPI_APPS_CLK_SRC 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define BLSP2_QUP2_I2C_APPS_CLK_SRC 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define BLSP2_QUP2_SPI_APPS_CLK_SRC 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define BLSP2_QUP3_I2C_APPS_CLK_SRC 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define BLSP2_QUP3_SPI_APPS_CLK_SRC 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define BLSP2_QUP4_I2C_APPS_CLK_SRC 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define BLSP2_QUP4_SPI_APPS_CLK_SRC 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define BLSP2_UART1_APPS_CLK_SRC 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define BLSP2_UART2_APPS_CLK_SRC 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define GCC_AGGRE2_UFS_AXI_CLK 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define GCC_AGGRE2_USB3_AXI_CLK 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define GCC_BIMC_GFX_CLK 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define GCC_BIMC_HMSS_AXI_CLK 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define GCC_BIMC_MSS_Q6_AXI_CLK 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define GCC_BLSP1_AHB_CLK 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define GCC_BLSP1_QUP1_I2C_APPS_CLK 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define GCC_BLSP1_QUP1_SPI_APPS_CLK 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define GCC_BLSP1_QUP2_I2C_APPS_CLK 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define GCC_BLSP1_QUP2_SPI_APPS_CLK 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define GCC_BLSP1_QUP3_I2C_APPS_CLK 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define GCC_BLSP1_QUP3_SPI_APPS_CLK 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define GCC_BLSP1_QUP4_I2C_APPS_CLK 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define GCC_BLSP1_QUP4_SPI_APPS_CLK 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define GCC_BLSP1_UART1_APPS_CLK 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define GCC_BLSP1_UART2_APPS_CLK 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define GCC_BLSP2_AHB_CLK 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define GCC_BLSP2_QUP1_I2C_APPS_CLK 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define GCC_BLSP2_QUP1_SPI_APPS_CLK 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define GCC_BLSP2_QUP2_I2C_APPS_CLK 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define GCC_BLSP2_QUP2_SPI_APPS_CLK 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define GCC_BLSP2_QUP3_I2C_APPS_CLK 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define GCC_BLSP2_QUP3_SPI_APPS_CLK 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define GCC_BLSP2_QUP4_I2C_APPS_CLK 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define GCC_BLSP2_QUP4_SPI_APPS_CLK 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define GCC_BLSP2_UART1_APPS_CLK 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define GCC_BLSP2_UART2_APPS_CLK 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define GCC_BOOT_ROM_AHB_CLK 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define GCC_CFG_NOC_USB2_AXI_CLK 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define GCC_CFG_NOC_USB3_AXI_CLK 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define GCC_DCC_AHB_CLK 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define GCC_GP1_CLK 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define GCC_GP2_CLK 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define GCC_GP3_CLK 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define GCC_GPU_BIMC_GFX_CLK 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define GCC_GPU_CFG_AHB_CLK 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define GCC_GPU_GPLL0_CLK 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define GCC_GPU_GPLL0_DIV_CLK 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define GCC_HMSS_DVM_BUS_CLK 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define GCC_HMSS_RBCPR_CLK 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define GCC_MMSS_GPLL0_CLK 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define GCC_MMSS_GPLL0_DIV_CLK 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define GCC_MMSS_NOC_CFG_AHB_CLK 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define GCC_MMSS_SYS_NOC_AXI_CLK 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define GCC_MSS_CFG_AHB_CLK 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define GCC_MSS_GPLL0_DIV_CLK 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define GCC_MSS_MNOC_BIMC_AXI_CLK 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define GCC_MSS_Q6_BIMC_AXI_CLK 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define GCC_MSS_SNOC_AXI_CLK 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define GCC_PDM2_CLK 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define GCC_PDM_AHB_CLK 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define GCC_PRNG_AHB_CLK 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define GCC_QSPI_AHB_CLK 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define GCC_QSPI_SER_CLK 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define GCC_SDCC1_AHB_CLK 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define GCC_SDCC1_APPS_CLK 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define GCC_SDCC1_ICE_CORE_CLK 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define GCC_SDCC2_AHB_CLK 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define GCC_SDCC2_APPS_CLK 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define GCC_UFS_AHB_CLK 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define GCC_UFS_AXI_CLK 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define GCC_UFS_CLKREF_CLK 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define GCC_UFS_ICE_CORE_CLK 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define GCC_UFS_PHY_AUX_CLK 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define GCC_UFS_RX_SYMBOL_0_CLK 84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define GCC_UFS_RX_SYMBOL_1_CLK 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define GCC_UFS_TX_SYMBOL_0_CLK 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define GCC_UFS_UNIPRO_CORE_CLK 87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define GCC_USB20_MASTER_CLK 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define GCC_USB20_MOCK_UTMI_CLK 89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define GCC_USB20_SLEEP_CLK 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define GCC_USB30_MASTER_CLK 91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define GCC_USB30_MOCK_UTMI_CLK 92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define GCC_USB30_SLEEP_CLK 93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define GCC_USB3_CLKREF_CLK 94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define GCC_USB3_PHY_AUX_CLK 95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define GCC_USB3_PHY_PIPE_CLK 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define GCC_USB_PHY_CFG_AHB2PHY_CLK 97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define GP1_CLK_SRC 98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define GP2_CLK_SRC 99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define GP3_CLK_SRC 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define GPLL0 101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define GPLL0_EARLY 102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define GPLL1 103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define GPLL1_EARLY 104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define GPLL4 105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define GPLL4_EARLY 106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define HMSS_GPLL0_CLK_SRC 107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define HMSS_GPLL4_CLK_SRC 108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define HMSS_RBCPR_CLK_SRC 109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define PDM2_CLK_SRC 110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define QSPI_SER_CLK_SRC 111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define SDCC1_APPS_CLK_SRC 112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define SDCC1_ICE_CORE_CLK_SRC 113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define SDCC2_APPS_CLK_SRC 114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define UFS_AXI_CLK_SRC 115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define UFS_ICE_CORE_CLK_SRC 116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define UFS_PHY_AUX_CLK_SRC 117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define UFS_UNIPRO_CORE_CLK_SRC 118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define USB20_MASTER_CLK_SRC 119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define USB20_MOCK_UTMI_CLK_SRC 120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define USB30_MASTER_CLK_SRC 121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define USB30_MOCK_UTMI_CLK_SRC 122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define USB3_PHY_AUX_CLK_SRC 123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define GPLL0_OUT_MSSCC 124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define GCC_UFS_AXI_HW_CTL_CLK 125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define GCC_UFS_ICE_CORE_HW_CTL_CLK 126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define GCC_UFS_PHY_AUX_HW_CTL_CLK 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define GCC_UFS_UNIPRO_CORE_HW_CTL_CLK 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define GCC_RX0_USB2_CLKREF_CLK 129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define GCC_RX1_USB2_CLKREF_CLK 130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define PCIE_0_GDSC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define UFS_GDSC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define USB_30_GDSC 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define GCC_QUSB2PHY_PRIM_BCR 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define GCC_QUSB2PHY_SEC_BCR 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define GCC_UFS_BCR 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define GCC_USB3_DP_PHY_BCR 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define GCC_USB3_PHY_BCR 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define GCC_USB3PHY_PHY_BCR 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define GCC_USB_20_BCR 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define GCC_USB_30_BCR 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define GCC_USB_PHY_CFG_AHB2PHY_BCR 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define GCC_MSS_RESTART 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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