^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef _DT_BINDINGS_CLK_QCOM_GCC_SC7180_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define _DT_BINDINGS_CLK_QCOM_GCC_SC7180_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) /* GCC clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define GCC_GPLL0_MAIN_DIV_CDIV 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define GPLL0 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define GPLL0_OUT_EVEN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define GPLL1 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define GPLL4 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define GPLL6 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define GPLL7 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define GCC_AGGRE_UFS_PHY_AXI_CLK 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define GCC_AGGRE_USB3_PRIM_AXI_CLK 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define GCC_BOOT_ROM_AHB_CLK 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define GCC_CAMERA_AHB_CLK 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define GCC_CAMERA_HF_AXI_CLK 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define GCC_CAMERA_THROTTLE_HF_AXI_CLK 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define GCC_CAMERA_XO_CLK 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define GCC_CE1_AHB_CLK 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define GCC_CE1_AXI_CLK 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define GCC_CE1_CLK 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define GCC_CPUSS_AHB_CLK 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define GCC_CPUSS_AHB_CLK_SRC 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define GCC_CPUSS_GNOC_CLK 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define GCC_CPUSS_RBCPR_CLK 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define GCC_DDRSS_GPU_AXI_CLK 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define GCC_DISP_AHB_CLK 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define GCC_DISP_GPLL0_CLK_SRC 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define GCC_DISP_GPLL0_DIV_CLK_SRC 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define GCC_DISP_HF_AXI_CLK 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define GCC_DISP_THROTTLE_HF_AXI_CLK 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define GCC_DISP_XO_CLK 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define GCC_GP1_CLK 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define GCC_GP1_CLK_SRC 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define GCC_GP2_CLK 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define GCC_GP2_CLK_SRC 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define GCC_GP3_CLK 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define GCC_GP3_CLK_SRC 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define GCC_GPU_CFG_AHB_CLK 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define GCC_GPU_GPLL0_CLK_SRC 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define GCC_GPU_GPLL0_DIV_CLK_SRC 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define GCC_GPU_MEMNOC_GFX_CLK 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define GCC_GPU_SNOC_DVM_GFX_CLK 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define GCC_NPU_AXI_CLK 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define GCC_NPU_BWMON_AXI_CLK 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define GCC_NPU_BWMON_DMA_CFG_AHB_CLK 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define GCC_NPU_BWMON_DSP_CFG_AHB_CLK 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define GCC_NPU_CFG_AHB_CLK 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define GCC_NPU_DMA_CLK 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define GCC_NPU_GPLL0_CLK_SRC 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define GCC_NPU_GPLL0_DIV_CLK_SRC 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define GCC_PDM2_CLK 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define GCC_PDM2_CLK_SRC 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define GCC_PDM_AHB_CLK 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define GCC_PDM_XO4_CLK 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define GCC_PRNG_AHB_CLK 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define GCC_QSPI_CNOC_PERIPH_AHB_CLK 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define GCC_QSPI_CORE_CLK 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define GCC_QSPI_CORE_CLK_SRC 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define GCC_QUPV3_WRAP0_CORE_2X_CLK 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define GCC_QUPV3_WRAP0_CORE_CLK 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define GCC_QUPV3_WRAP0_S0_CLK 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define GCC_QUPV3_WRAP0_S0_CLK_SRC 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define GCC_QUPV3_WRAP0_S1_CLK 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define GCC_QUPV3_WRAP0_S1_CLK_SRC 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define GCC_QUPV3_WRAP0_S2_CLK 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define GCC_QUPV3_WRAP0_S2_CLK_SRC 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define GCC_QUPV3_WRAP0_S3_CLK 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define GCC_QUPV3_WRAP0_S3_CLK_SRC 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define GCC_QUPV3_WRAP0_S4_CLK 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define GCC_QUPV3_WRAP0_S4_CLK_SRC 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define GCC_QUPV3_WRAP0_S5_CLK 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define GCC_QUPV3_WRAP0_S5_CLK_SRC 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define GCC_QUPV3_WRAP1_CORE_2X_CLK 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define GCC_QUPV3_WRAP1_CORE_CLK 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define GCC_QUPV3_WRAP1_S0_CLK 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define GCC_QUPV3_WRAP1_S0_CLK_SRC 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define GCC_QUPV3_WRAP1_S1_CLK 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define GCC_QUPV3_WRAP1_S1_CLK_SRC 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define GCC_QUPV3_WRAP1_S2_CLK 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define GCC_QUPV3_WRAP1_S2_CLK_SRC 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define GCC_QUPV3_WRAP1_S3_CLK 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define GCC_QUPV3_WRAP1_S3_CLK_SRC 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define GCC_QUPV3_WRAP1_S4_CLK 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define GCC_QUPV3_WRAP1_S4_CLK_SRC 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define GCC_QUPV3_WRAP1_S5_CLK 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define GCC_QUPV3_WRAP1_S5_CLK_SRC 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define GCC_QUPV3_WRAP_0_M_AHB_CLK 84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define GCC_QUPV3_WRAP_0_S_AHB_CLK 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define GCC_QUPV3_WRAP_1_M_AHB_CLK 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define GCC_QUPV3_WRAP_1_S_AHB_CLK 87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define GCC_SDCC1_AHB_CLK 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define GCC_SDCC1_APPS_CLK 89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define GCC_SDCC1_APPS_CLK_SRC 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define GCC_SDCC1_ICE_CORE_CLK 91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define GCC_SDCC1_ICE_CORE_CLK_SRC 92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define GCC_SDCC2_AHB_CLK 93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define GCC_SDCC2_APPS_CLK 94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define GCC_SDCC2_APPS_CLK_SRC 95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define GCC_SYS_NOC_CPUSS_AHB_CLK 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define GCC_UFS_MEM_CLKREF_CLK 97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define GCC_UFS_PHY_AHB_CLK 98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define GCC_UFS_PHY_AXI_CLK 99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define GCC_UFS_PHY_AXI_CLK_SRC 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define GCC_UFS_PHY_ICE_CORE_CLK 101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define GCC_UFS_PHY_ICE_CORE_CLK_SRC 102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define GCC_UFS_PHY_PHY_AUX_CLK 103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define GCC_UFS_PHY_PHY_AUX_CLK_SRC 104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define GCC_UFS_PHY_RX_SYMBOL_0_CLK 105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define GCC_UFS_PHY_TX_SYMBOL_0_CLK 106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define GCC_UFS_PHY_UNIPRO_CORE_CLK 107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define GCC_USB30_PRIM_MASTER_CLK 109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define GCC_USB30_PRIM_MASTER_CLK_SRC 110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define GCC_USB30_PRIM_MOCK_UTMI_CLK 111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define GCC_USB30_PRIM_SLEEP_CLK 113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define GCC_USB3_PRIM_CLKREF_CLK 114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define GCC_USB3_PRIM_PHY_AUX_CLK 115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define GCC_USB3_PRIM_PHY_COM_AUX_CLK 117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define GCC_USB3_PRIM_PHY_PIPE_CLK 118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define GCC_USB_PHY_CFG_AHB2PHY_CLK 119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define GCC_VIDEO_AHB_CLK 120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define GCC_VIDEO_AXI_CLK 121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define GCC_VIDEO_GPLL0_DIV_CLK_SRC 122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define GCC_VIDEO_THROTTLE_AXI_CLK 123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define GCC_VIDEO_XO_CLK 124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define GCC_MSS_CFG_AHB_CLK 125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define GCC_MSS_MFAB_AXIS_CLK 126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define GCC_MSS_NAV_AXI_CLK 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define GCC_MSS_Q6_MEMNOC_AXI_CLK 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define GCC_MSS_SNOC_AXI_CLK 129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define GCC_SEC_CTRL_CLK_SRC 130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define GCC_LPASS_CFG_NOC_SWAY_CLK 131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* GCC resets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define GCC_QUSB2PHY_PRIM_BCR 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define GCC_QUSB2PHY_SEC_BCR 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define GCC_UFS_PHY_BCR 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define GCC_USB30_PRIM_BCR 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define GCC_USB3_DP_PHY_PRIM_BCR 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define GCC_USB3_DP_PHY_SEC_BCR 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define GCC_USB3_PHY_PRIM_BCR 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define GCC_USB3_PHY_SEC_BCR 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define GCC_USB3PHY_PHY_PRIM_BCR 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define GCC_USB3PHY_PHY_SEC_BCR 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define GCC_USB_PHY_CFG_AHB2PHY_BCR 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* GCC GDSCRs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define UFS_PHY_GDSC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define USB30_PRIM_GDSC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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