Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2018, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #ifndef _DT_BINDINGS_CLK_QCOM_GCC_QCS404_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #define _DT_BINDINGS_CLK_QCOM_GCC_QCS404_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #define GCC_APSS_AHB_CLK_SRC				0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #define GCC_BLSP1_QUP0_I2C_APPS_CLK_SRC			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define GCC_BLSP1_QUP0_SPI_APPS_CLK_SRC			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define GCC_BLSP1_QUP1_I2C_APPS_CLK_SRC			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define GCC_BLSP1_QUP2_I2C_APPS_CLK_SRC			5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC			6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define GCC_BLSP1_QUP3_I2C_APPS_CLK_SRC			7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC			8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define GCC_BLSP1_QUP4_I2C_APPS_CLK_SRC			9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define GCC_BLSP1_QUP4_SPI_APPS_CLK_SRC			10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define GCC_BLSP1_UART0_APPS_CLK_SRC			11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define GCC_BLSP1_UART1_APPS_CLK_SRC			12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define GCC_BLSP1_UART2_APPS_CLK_SRC			13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define GCC_BLSP1_UART3_APPS_CLK_SRC			14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define GCC_BLSP2_QUP0_I2C_APPS_CLK_SRC			15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define GCC_BLSP2_QUP0_SPI_APPS_CLK_SRC			16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define GCC_BLSP2_UART0_APPS_CLK_SRC			17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define GCC_BYTE0_CLK_SRC				18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define GCC_EMAC_CLK_SRC				19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define GCC_EMAC_PTP_CLK_SRC				20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define GCC_ESC0_CLK_SRC				21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define GCC_APSS_AHB_CLK				22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define GCC_APSS_AXI_CLK				23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define GCC_BIMC_APSS_AXI_CLK				24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define GCC_BIMC_GFX_CLK				25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define GCC_BIMC_MDSS_CLK				26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define GCC_BLSP1_AHB_CLK				27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define GCC_BLSP1_QUP0_I2C_APPS_CLK			28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define GCC_BLSP1_QUP0_SPI_APPS_CLK			29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define GCC_BLSP1_QUP1_I2C_APPS_CLK			30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define GCC_BLSP1_QUP1_SPI_APPS_CLK			31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define GCC_BLSP1_QUP2_I2C_APPS_CLK			32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define GCC_BLSP1_QUP2_SPI_APPS_CLK			33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define GCC_BLSP1_QUP3_I2C_APPS_CLK			34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define GCC_BLSP1_QUP3_SPI_APPS_CLK			35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define GCC_BLSP1_QUP4_I2C_APPS_CLK			36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define GCC_BLSP1_QUP4_SPI_APPS_CLK			37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define GCC_BLSP1_UART0_APPS_CLK			38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define GCC_BLSP1_UART1_APPS_CLK			39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define GCC_BLSP1_UART2_APPS_CLK			40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define GCC_BLSP1_UART3_APPS_CLK			41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define GCC_BLSP2_AHB_CLK				42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define GCC_BLSP2_QUP0_I2C_APPS_CLK			43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define GCC_BLSP2_QUP0_SPI_APPS_CLK			44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define GCC_BLSP2_UART0_APPS_CLK			45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define GCC_BOOT_ROM_AHB_CLK				46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define GCC_DCC_CLK					47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define GCC_GENI_IR_H_CLK				48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define GCC_ETH_AXI_CLK					49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define GCC_ETH_PTP_CLK					50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define GCC_ETH_RGMII_CLK				51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define GCC_ETH_SLAVE_AHB_CLK				52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define GCC_GENI_IR_S_CLK				53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define GCC_GP1_CLK					54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define GCC_GP2_CLK					55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define GCC_GP3_CLK					56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define GCC_MDSS_AHB_CLK				57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define GCC_MDSS_AXI_CLK				58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define GCC_MDSS_BYTE0_CLK				59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define GCC_MDSS_ESC0_CLK				60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define GCC_MDSS_HDMI_APP_CLK				61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define GCC_MDSS_HDMI_PCLK_CLK				62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define GCC_MDSS_MDP_CLK				63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define GCC_MDSS_PCLK0_CLK				64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define GCC_MDSS_VSYNC_CLK				65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define GCC_OXILI_AHB_CLK				66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define GCC_OXILI_GFX3D_CLK				67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define GCC_PCIE_0_AUX_CLK				68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define GCC_PCIE_0_CFG_AHB_CLK				69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define GCC_PCIE_0_MSTR_AXI_CLK				70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define GCC_PCIE_0_PIPE_CLK				71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define GCC_PCIE_0_SLV_AXI_CLK				72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define GCC_PCNOC_USB2_CLK				73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define GCC_PCNOC_USB3_CLK				74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define GCC_PDM2_CLK					75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define GCC_PDM_AHB_CLK					76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define GCC_VSYNC_CLK_SRC				77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define GCC_PRNG_AHB_CLK				78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define GCC_PWM0_XO512_CLK				79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define GCC_PWM1_XO512_CLK				80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define GCC_PWM2_XO512_CLK				81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define GCC_SDCC1_AHB_CLK				82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define GCC_SDCC1_APPS_CLK				83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define GCC_SDCC1_ICE_CORE_CLK				84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define GCC_SDCC2_AHB_CLK				85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define GCC_SDCC2_APPS_CLK				86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define GCC_SYS_NOC_USB3_CLK				87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define GCC_USB20_MOCK_UTMI_CLK				88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define GCC_USB2A_PHY_SLEEP_CLK				89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define GCC_USB30_MASTER_CLK				90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define GCC_USB30_MOCK_UTMI_CLK				91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define GCC_USB30_SLEEP_CLK				92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define GCC_USB3_PHY_AUX_CLK				93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define GCC_USB3_PHY_PIPE_CLK				94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define GCC_USB_HS_PHY_CFG_AHB_CLK			95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define GCC_USB_HS_SYSTEM_CLK				96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define GCC_GFX3D_CLK_SRC				97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define GCC_GP1_CLK_SRC					98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define GCC_GP2_CLK_SRC					99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define GCC_GP3_CLK_SRC					100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define GCC_GPLL0_OUT_MAIN				101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define GCC_GPLL1_OUT_MAIN				102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define GCC_GPLL3_OUT_MAIN				103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define GCC_GPLL4_OUT_MAIN				104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define GCC_HDMI_APP_CLK_SRC				105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define GCC_HDMI_PCLK_CLK_SRC				106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define GCC_MDP_CLK_SRC					107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define GCC_PCIE_0_AUX_CLK_SRC				108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define GCC_PCIE_0_PIPE_CLK_SRC				109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define GCC_PCLK0_CLK_SRC				110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define GCC_PDM2_CLK_SRC				111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define GCC_SDCC1_APPS_CLK_SRC				112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define GCC_SDCC1_ICE_CORE_CLK_SRC			113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define GCC_SDCC2_APPS_CLK_SRC				114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define GCC_USB20_MOCK_UTMI_CLK_SRC			115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define GCC_USB30_MASTER_CLK_SRC			116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define GCC_USB30_MOCK_UTMI_CLK_SRC			117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define GCC_USB3_PHY_AUX_CLK_SRC			118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define GCC_USB_HS_SYSTEM_CLK_SRC			119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define GCC_GPLL0_AO_CLK_SRC				120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define GCC_USB_HS_INACTIVITY_TIMERS_CLK		122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define GCC_GPLL0_AO_OUT_MAIN				123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define GCC_GPLL0_SLEEP_CLK_SRC				124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define GCC_GPLL6					125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define GCC_GPLL6_OUT_AUX				126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define GCC_MDSS_MDP_VOTE_CLK				127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define GCC_MDSS_ROTATOR_VOTE_CLK			128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define GCC_BIMC_GPU_CLK				129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define GCC_GTCU_AHB_CLK				130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define GCC_GFX_TCU_CLK					131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define GCC_GFX_TBU_CLK					132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define GCC_SMMU_CFG_CLK				133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define GCC_APSS_TCU_CLK				134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define GCC_CRYPTO_AHB_CLK				135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define GCC_CRYPTO_AXI_CLK				136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define GCC_CRYPTO_CLK					137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define GCC_MDP_TBU_CLK					138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define GCC_QDSS_DAP_CLK				139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define GCC_DCC_XO_CLK					140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define GCC_WCSS_Q6_AHB_CLK				141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define GCC_WCSS_Q6_AXIM_CLK				142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define GCC_CDSP_CFG_AHB_CLK				143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define GCC_BIMC_CDSP_CLK				144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define GCC_CDSP_TBU_CLK				145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define GCC_CDSP_BIMC_CLK_SRC				146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define GCC_GENI_IR_BCR					0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define GCC_USB_HS_BCR					1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define GCC_USB2_HS_PHY_ONLY_BCR			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define GCC_QUSB2_PHY_BCR				3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define GCC_USB_HS_PHY_CFG_AHB_BCR			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define GCC_USB2A_PHY_BCR				5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define GCC_USB3_PHY_BCR				6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define GCC_USB_30_BCR					7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define GCC_USB3PHY_PHY_BCR				8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define GCC_PCIE_0_BCR					9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define GCC_PCIE_0_PHY_BCR				10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define GCC_PCIE_0_LINK_DOWN_BCR			11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define GCC_PCIEPHY_0_PHY_BCR				12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define GCC_EMAC_BCR					13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define GCC_CDSP_RESTART				14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define GCC_PCIE_0_AXI_MASTER_STICKY_ARES		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define GCC_PCIE_0_AHB_ARES				16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define GCC_PCIE_0_AXI_SLAVE_ARES			17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define GCC_PCIE_0_AXI_MASTER_ARES			18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define GCC_PCIE_0_CORE_STICKY_ARES			19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define GCC_PCIE_0_SLEEP_ARES				20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define GCC_PCIE_0_PIPE_ARES				21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define GCC_WDSP_RESTART				22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #endif