Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2016, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #ifndef _DT_BINDINGS_CLK_MSM_GCC_COBALT_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #define _DT_BINDINGS_CLK_MSM_GCC_COBALT_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #define BLSP1_QUP1_I2C_APPS_CLK_SRC				0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #define BLSP1_QUP1_SPI_APPS_CLK_SRC				1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define BLSP1_QUP2_I2C_APPS_CLK_SRC				2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define BLSP1_QUP2_SPI_APPS_CLK_SRC				3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define BLSP1_QUP3_I2C_APPS_CLK_SRC				4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define BLSP1_QUP3_SPI_APPS_CLK_SRC				5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define BLSP1_QUP4_I2C_APPS_CLK_SRC				6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define BLSP1_QUP4_SPI_APPS_CLK_SRC				7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define BLSP1_QUP5_I2C_APPS_CLK_SRC				8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define BLSP1_QUP5_SPI_APPS_CLK_SRC				9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define BLSP1_QUP6_I2C_APPS_CLK_SRC				10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define BLSP1_QUP6_SPI_APPS_CLK_SRC				11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define BLSP1_UART1_APPS_CLK_SRC				12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define BLSP1_UART2_APPS_CLK_SRC				13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define BLSP1_UART3_APPS_CLK_SRC				14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define BLSP2_QUP1_I2C_APPS_CLK_SRC				15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define BLSP2_QUP1_SPI_APPS_CLK_SRC				16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define BLSP2_QUP2_I2C_APPS_CLK_SRC				17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define BLSP2_QUP2_SPI_APPS_CLK_SRC				18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define BLSP2_QUP3_I2C_APPS_CLK_SRC				19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define BLSP2_QUP3_SPI_APPS_CLK_SRC				20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define BLSP2_QUP4_I2C_APPS_CLK_SRC				21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define BLSP2_QUP4_SPI_APPS_CLK_SRC				22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define BLSP2_QUP5_I2C_APPS_CLK_SRC				23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define BLSP2_QUP5_SPI_APPS_CLK_SRC				24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define BLSP2_QUP6_I2C_APPS_CLK_SRC				25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define BLSP2_QUP6_SPI_APPS_CLK_SRC				26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define BLSP2_UART1_APPS_CLK_SRC				27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define BLSP2_UART2_APPS_CLK_SRC				28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define BLSP2_UART3_APPS_CLK_SRC				29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define GCC_AGGRE1_NOC_XO_CLK					30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define GCC_AGGRE1_UFS_AXI_CLK					31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define GCC_AGGRE1_USB3_AXI_CLK					32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define GCC_APSS_QDSS_TSCTR_DIV2_CLK				33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define GCC_APSS_QDSS_TSCTR_DIV8_CLK				34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define GCC_BIMC_HMSS_AXI_CLK					35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define GCC_BIMC_MSS_Q6_AXI_CLK					36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define GCC_BLSP1_AHB_CLK					37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define GCC_BLSP1_QUP1_I2C_APPS_CLK				38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define GCC_BLSP1_QUP1_SPI_APPS_CLK				39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define GCC_BLSP1_QUP2_I2C_APPS_CLK				40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define GCC_BLSP1_QUP2_SPI_APPS_CLK				41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define GCC_BLSP1_QUP3_I2C_APPS_CLK				42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define GCC_BLSP1_QUP3_SPI_APPS_CLK				43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define GCC_BLSP1_QUP4_I2C_APPS_CLK				44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define GCC_BLSP1_QUP4_SPI_APPS_CLK				45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define GCC_BLSP1_QUP5_I2C_APPS_CLK				46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define GCC_BLSP1_QUP5_SPI_APPS_CLK				47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define GCC_BLSP1_QUP6_I2C_APPS_CLK				48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define GCC_BLSP1_QUP6_SPI_APPS_CLK				49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define GCC_BLSP1_SLEEP_CLK					50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define GCC_BLSP1_UART1_APPS_CLK				51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define GCC_BLSP1_UART2_APPS_CLK				52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define GCC_BLSP1_UART3_APPS_CLK				53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define GCC_BLSP2_AHB_CLK					54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define GCC_BLSP2_QUP1_I2C_APPS_CLK				55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define GCC_BLSP2_QUP1_SPI_APPS_CLK				56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define GCC_BLSP2_QUP2_I2C_APPS_CLK				57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define GCC_BLSP2_QUP2_SPI_APPS_CLK				58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define GCC_BLSP2_QUP3_I2C_APPS_CLK				59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define GCC_BLSP2_QUP3_SPI_APPS_CLK				60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define GCC_BLSP2_QUP4_I2C_APPS_CLK				61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define GCC_BLSP2_QUP4_SPI_APPS_CLK				62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define GCC_BLSP2_QUP5_I2C_APPS_CLK				63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define GCC_BLSP2_QUP5_SPI_APPS_CLK				64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define GCC_BLSP2_QUP6_I2C_APPS_CLK				65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define GCC_BLSP2_QUP6_SPI_APPS_CLK				66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define GCC_BLSP2_SLEEP_CLK					67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define GCC_BLSP2_UART1_APPS_CLK				68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define GCC_BLSP2_UART2_APPS_CLK				69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define GCC_BLSP2_UART3_APPS_CLK				70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define GCC_CFG_NOC_USB3_AXI_CLK				71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define GCC_GP1_CLK						72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define GCC_GP2_CLK						73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define GCC_GP3_CLK						74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define GCC_GPU_BIMC_GFX_CLK					75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define GCC_GPU_BIMC_GFX_SRC_CLK				76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define GCC_GPU_CFG_AHB_CLK					77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define GCC_GPU_SNOC_DVM_GFX_CLK				78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define GCC_HMSS_AHB_CLK					79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define GCC_HMSS_AT_CLK						80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define GCC_HMSS_DVM_BUS_CLK					81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define GCC_HMSS_RBCPR_CLK					82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define GCC_HMSS_TRIG_CLK					83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define GCC_LPASS_AT_CLK					84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define GCC_LPASS_TRIG_CLK					85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define GCC_MMSS_NOC_CFG_AHB_CLK				86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define GCC_MMSS_QM_AHB_CLK					87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define GCC_MMSS_QM_CORE_CLK					88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define GCC_MMSS_SYS_NOC_AXI_CLK				89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define GCC_MSS_AT_CLK						90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define GCC_PCIE_0_AUX_CLK					91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define GCC_PCIE_0_CFG_AHB_CLK					92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define GCC_PCIE_0_MSTR_AXI_CLK					93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define GCC_PCIE_0_PIPE_CLK					94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define GCC_PCIE_0_SLV_AXI_CLK					95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define GCC_PCIE_PHY_AUX_CLK					96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define GCC_PDM2_CLK						97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define GCC_PDM_AHB_CLK						98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define GCC_PDM_XO4_CLK						99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define GCC_PRNG_AHB_CLK					100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define GCC_SDCC2_AHB_CLK					101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define GCC_SDCC2_APPS_CLK					102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define GCC_SDCC4_AHB_CLK					103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define GCC_SDCC4_APPS_CLK					104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define GCC_TSIF_AHB_CLK					105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define GCC_TSIF_INACTIVITY_TIMERS_CLK				106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define GCC_TSIF_REF_CLK					107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define GCC_UFS_AHB_CLK						108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define GCC_UFS_AXI_CLK						109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define GCC_UFS_ICE_CORE_CLK					110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define GCC_UFS_PHY_AUX_CLK					111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define GCC_UFS_RX_SYMBOL_0_CLK					112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define GCC_UFS_RX_SYMBOL_1_CLK					113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define GCC_UFS_TX_SYMBOL_0_CLK					114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define GCC_UFS_UNIPRO_CORE_CLK					115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define GCC_USB30_MASTER_CLK					116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define GCC_USB30_MOCK_UTMI_CLK					117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define GCC_USB30_SLEEP_CLK					118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define GCC_USB3_PHY_AUX_CLK					119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define GCC_USB3_PHY_PIPE_CLK					120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define GCC_USB_PHY_CFG_AHB2PHY_CLK				121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define GP1_CLK_SRC						122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define GP2_CLK_SRC						123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define GP3_CLK_SRC						124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define GPLL0							125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define GPLL0_OUT_EVEN						126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define GPLL0_OUT_MAIN						127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define GPLL0_OUT_ODD						128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define GPLL0_OUT_TEST						129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define GPLL1							130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define GPLL1_OUT_EVEN						131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define GPLL1_OUT_MAIN						132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define GPLL1_OUT_ODD						133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define GPLL1_OUT_TEST						134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define GPLL2							135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define GPLL2_OUT_EVEN						136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define GPLL2_OUT_MAIN						137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define GPLL2_OUT_ODD						138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define GPLL2_OUT_TEST						139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define GPLL3							140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define GPLL3_OUT_EVEN						141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define GPLL3_OUT_MAIN						142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define GPLL3_OUT_ODD						143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define GPLL3_OUT_TEST						144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define GPLL4							145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define GPLL4_OUT_EVEN						146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define GPLL4_OUT_MAIN						147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define GPLL4_OUT_ODD						148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define GPLL4_OUT_TEST						149
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define GPLL6							150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define GPLL6_OUT_EVEN						151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define GPLL6_OUT_MAIN						152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define GPLL6_OUT_ODD						153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define GPLL6_OUT_TEST						154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define HMSS_AHB_CLK_SRC					155
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define HMSS_RBCPR_CLK_SRC					156
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define PCIE_AUX_CLK_SRC					157
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define PDM2_CLK_SRC						158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define SDCC2_APPS_CLK_SRC					159
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define SDCC4_APPS_CLK_SRC					160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define TSIF_REF_CLK_SRC					161
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define UFS_AXI_CLK_SRC						162
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define USB30_MASTER_CLK_SRC					163
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define USB30_MOCK_UTMI_CLK_SRC					164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define USB3_PHY_AUX_CLK_SRC					165
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define GCC_USB3_CLKREF_CLK					166
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define GCC_HDMI_CLKREF_CLK					167
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define GCC_UFS_CLKREF_CLK					168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define GCC_PCIE_CLKREF_CLK					169
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define GCC_RX1_USB2_CLKREF_CLK					170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define GCC_MSS_CFG_AHB_CLK					171
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define GCC_BOOT_ROM_AHB_CLK					172
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define GCC_MSS_GPLL0_DIV_CLK_SRC				173
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define GCC_MSS_SNOC_AXI_CLK					174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define GCC_MSS_MNOC_BIMC_AXI_CLK				175
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define GCC_BIMC_GFX_CLK					176
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define UFS_UNIPRO_CORE_CLK_SRC					177
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define PCIE_0_GDSC						0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define UFS_GDSC						1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define USB_30_GDSC						2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define GCC_BLSP1_QUP1_BCR					0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define GCC_BLSP1_QUP2_BCR					1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define GCC_BLSP1_QUP3_BCR					2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define GCC_BLSP1_QUP4_BCR					3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define GCC_BLSP1_QUP5_BCR					4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define GCC_BLSP1_QUP6_BCR					5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define GCC_BLSP2_QUP1_BCR					6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define GCC_BLSP2_QUP2_BCR					7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define GCC_BLSP2_QUP3_BCR					8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define GCC_BLSP2_QUP4_BCR					9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define GCC_BLSP2_QUP5_BCR					10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define GCC_BLSP2_QUP6_BCR					11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define GCC_PCIE_0_BCR						12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define GCC_PDM_BCR						13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define GCC_SDCC2_BCR						14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define GCC_SDCC4_BCR						15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define GCC_TSIF_BCR						16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define GCC_UFS_BCR						17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define GCC_USB_30_BCR						18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define GCC_SYSTEM_NOC_BCR					19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define GCC_CONFIG_NOC_BCR					20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define GCC_AHB2PHY_EAST_BCR					21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define GCC_IMEM_BCR						22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define GCC_PIMEM_BCR						23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define GCC_MMSS_BCR						24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define GCC_QDSS_BCR						25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define GCC_WCSS_BCR						26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define GCC_BLSP1_BCR						27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define GCC_BLSP1_UART1_BCR					28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define GCC_BLSP1_UART2_BCR					29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define GCC_BLSP1_UART3_BCR					30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define GCC_CM_PHY_REFGEN1_BCR					31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define GCC_CM_PHY_REFGEN2_BCR					32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define GCC_BLSP2_BCR						33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define GCC_BLSP2_UART1_BCR					34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define GCC_BLSP2_UART2_BCR					35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define GCC_BLSP2_UART3_BCR					36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define GCC_SRAM_SENSOR_BCR					37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define GCC_PRNG_BCR						38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define GCC_TSIF_0_RESET					39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define GCC_TSIF_1_RESET					40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define GCC_TCSR_BCR						41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define GCC_BOOT_ROM_BCR					42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define GCC_MSG_RAM_BCR						43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define GCC_TLMM_BCR						44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define GCC_MPM_BCR						45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define GCC_SEC_CTRL_BCR					46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define GCC_SPMI_BCR						47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define GCC_SPDM_BCR						48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define GCC_CE1_BCR						49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define GCC_BIMC_BCR						50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define GCC_SNOC_BUS_TIMEOUT0_BCR				51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define GCC_SNOC_BUS_TIMEOUT1_BCR				52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define GCC_SNOC_BUS_TIMEOUT3_BCR				53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR				54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define GCC_PNOC_BUS_TIMEOUT0_BCR				55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define GCC_CNOC_PERIPH_BUS_TIMEOUT1_BCR			56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define GCC_CNOC_PERIPH_BUS_TIMEOUT2_BCR			57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define GCC_CNOC_BUS_TIMEOUT0_BCR				58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define GCC_CNOC_BUS_TIMEOUT1_BCR				59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define GCC_CNOC_BUS_TIMEOUT2_BCR				60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define GCC_CNOC_BUS_TIMEOUT3_BCR				61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define GCC_CNOC_BUS_TIMEOUT4_BCR				62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define GCC_CNOC_BUS_TIMEOUT5_BCR				63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define GCC_CNOC_BUS_TIMEOUT6_BCR				64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define GCC_CNOC_BUS_TIMEOUT7_BCR				65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define GCC_APB2JTAG_BCR					66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define GCC_RBCPR_CX_BCR					67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define GCC_RBCPR_MX_BCR					68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define GCC_USB3_PHY_BCR					69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define GCC_USB3PHY_PHY_BCR					70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define GCC_USB3_DP_PHY_BCR					71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define GCC_SSC_BCR						72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define GCC_SSC_RESET						73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define GCC_USB_PHY_CFG_AHB2PHY_BCR				74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define GCC_PCIE_0_LINK_DOWN_BCR				75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define GCC_PCIE_0_PHY_BCR					76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define GCC_PCIE_0_NOCSR_COM_PHY_BCR				77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define GCC_PCIE_PHY_BCR					78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define GCC_PCIE_PHY_NOCSR_COM_PHY_BCR				79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define GCC_PCIE_PHY_CFG_AHB_BCR				80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define GCC_PCIE_PHY_COM_BCR					81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define GCC_GPU_BCR						82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define GCC_SPSS_BCR						83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define GCC_OBT_ODT_BCR						84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define GCC_VS_BCR						85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define GCC_MSS_VS_RESET					86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define GCC_GPU_VS_RESET					87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define GCC_APC0_VS_RESET					88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define GCC_APC1_VS_RESET					89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define GCC_CNOC_BUS_TIMEOUT8_BCR				90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define GCC_CNOC_BUS_TIMEOUT9_BCR				91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define GCC_CNOC_BUS_TIMEOUT10_BCR				92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define GCC_CNOC_BUS_TIMEOUT11_BCR				93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define GCC_CNOC_BUS_TIMEOUT12_BCR				94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define GCC_CNOC_BUS_TIMEOUT13_BCR				95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define GCC_CNOC_BUS_TIMEOUT14_BCR				96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR				97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define GCC_AGGRE1_NOC_BCR					98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define GCC_AGGRE2_NOC_BCR					99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define GCC_DCC_BCR						100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define GCC_QREFS_VBG_CAL_BCR					101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define GCC_IPA_BCR						102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define GCC_GLM_BCR						103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define GCC_SKL_BCR						104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define GCC_MSMPU_BCR						105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define GCC_QUSB2PHY_PRIM_BCR					106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define GCC_QUSB2PHY_SEC_BCR					107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define GCC_MSS_RESTART						108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #endif