^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2016, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef _DT_BINDINGS_CLK_MSM_GCC_8994_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define _DT_BINDINGS_CLK_MSM_GCC_8994_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define GPLL0_EARLY 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define GPLL0 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define GPLL4_EARLY 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define GPLL4 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define UFS_AXI_CLK_SRC 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define USB30_MASTER_CLK_SRC 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define BLSP1_QUP1_I2C_APPS_CLK_SRC 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define BLSP1_QUP1_SPI_APPS_CLK_SRC 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define BLSP1_QUP2_I2C_APPS_CLK_SRC 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define BLSP1_QUP2_SPI_APPS_CLK_SRC 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define BLSP1_QUP3_I2C_APPS_CLK_SRC 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define BLSP1_QUP3_SPI_APPS_CLK_SRC 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define BLSP1_QUP4_I2C_APPS_CLK_SRC 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define BLSP1_QUP4_SPI_APPS_CLK_SRC 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define BLSP1_QUP5_I2C_APPS_CLK_SRC 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define BLSP1_QUP5_SPI_APPS_CLK_SRC 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define BLSP1_QUP6_I2C_APPS_CLK_SRC 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define BLSP1_QUP6_SPI_APPS_CLK_SRC 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define BLSP1_UART1_APPS_CLK_SRC 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define BLSP1_UART2_APPS_CLK_SRC 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define BLSP1_UART3_APPS_CLK_SRC 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define BLSP1_UART4_APPS_CLK_SRC 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define BLSP1_UART5_APPS_CLK_SRC 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define BLSP1_UART6_APPS_CLK_SRC 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define BLSP2_QUP1_I2C_APPS_CLK_SRC 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define BLSP2_QUP1_SPI_APPS_CLK_SRC 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define BLSP2_QUP2_I2C_APPS_CLK_SRC 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define BLSP2_QUP2_SPI_APPS_CLK_SRC 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define BLSP2_QUP3_I2C_APPS_CLK_SRC 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define BLSP2_QUP3_SPI_APPS_CLK_SRC 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define BLSP2_QUP4_I2C_APPS_CLK_SRC 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define BLSP2_QUP4_SPI_APPS_CLK_SRC 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define BLSP2_QUP5_I2C_APPS_CLK_SRC 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define BLSP2_QUP5_SPI_APPS_CLK_SRC 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define BLSP2_QUP6_I2C_APPS_CLK_SRC 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define BLSP2_QUP6_SPI_APPS_CLK_SRC 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define BLSP2_UART1_APPS_CLK_SRC 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define BLSP2_UART2_APPS_CLK_SRC 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define BLSP2_UART3_APPS_CLK_SRC 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define BLSP2_UART4_APPS_CLK_SRC 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define BLSP2_UART5_APPS_CLK_SRC 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define BLSP2_UART6_APPS_CLK_SRC 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define GP1_CLK_SRC 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define GP2_CLK_SRC 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define GP3_CLK_SRC 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PCIE_0_AUX_CLK_SRC 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PCIE_0_PIPE_CLK_SRC 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PCIE_1_AUX_CLK_SRC 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PCIE_1_PIPE_CLK_SRC 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PDM2_CLK_SRC 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SDCC1_APPS_CLK_SRC 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SDCC2_APPS_CLK_SRC 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SDCC3_APPS_CLK_SRC 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SDCC4_APPS_CLK_SRC 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define TSIF_REF_CLK_SRC 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define USB30_MOCK_UTMI_CLK_SRC 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define USB3_PHY_AUX_CLK_SRC 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define USB_HS_SYSTEM_CLK_SRC 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define GCC_BLSP1_AHB_CLK 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define GCC_BLSP1_QUP1_I2C_APPS_CLK 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define GCC_BLSP1_QUP1_SPI_APPS_CLK 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define GCC_BLSP1_QUP2_I2C_APPS_CLK 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define GCC_BLSP1_QUP2_SPI_APPS_CLK 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define GCC_BLSP1_QUP3_I2C_APPS_CLK 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define GCC_BLSP1_QUP3_SPI_APPS_CLK 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define GCC_BLSP1_QUP4_I2C_APPS_CLK 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define GCC_BLSP1_QUP4_SPI_APPS_CLK 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define GCC_BLSP1_QUP5_I2C_APPS_CLK 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define GCC_BLSP1_QUP5_SPI_APPS_CLK 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define GCC_BLSP1_QUP6_I2C_APPS_CLK 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define GCC_BLSP1_QUP6_SPI_APPS_CLK 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define GCC_BLSP1_UART1_APPS_CLK 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define GCC_BLSP1_UART2_APPS_CLK 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define GCC_BLSP1_UART3_APPS_CLK 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define GCC_BLSP1_UART4_APPS_CLK 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define GCC_BLSP1_UART5_APPS_CLK 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define GCC_BLSP1_UART6_APPS_CLK 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define GCC_BLSP2_AHB_CLK 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define GCC_BLSP2_QUP1_I2C_APPS_CLK 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define GCC_BLSP2_QUP1_SPI_APPS_CLK 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define GCC_BLSP2_QUP2_I2C_APPS_CLK 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define GCC_BLSP2_QUP2_SPI_APPS_CLK 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define GCC_BLSP2_QUP3_I2C_APPS_CLK 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define GCC_BLSP2_QUP3_SPI_APPS_CLK 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define GCC_BLSP2_QUP4_I2C_APPS_CLK 84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define GCC_BLSP2_QUP4_SPI_APPS_CLK 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define GCC_BLSP2_QUP5_I2C_APPS_CLK 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define GCC_BLSP2_QUP5_SPI_APPS_CLK 87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define GCC_BLSP2_QUP6_I2C_APPS_CLK 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define GCC_BLSP2_QUP6_SPI_APPS_CLK 89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define GCC_BLSP2_UART1_APPS_CLK 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define GCC_BLSP2_UART2_APPS_CLK 91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define GCC_BLSP2_UART3_APPS_CLK 92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define GCC_BLSP2_UART4_APPS_CLK 93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define GCC_BLSP2_UART5_APPS_CLK 94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define GCC_BLSP2_UART6_APPS_CLK 95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define GCC_GP1_CLK 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define GCC_GP2_CLK 97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define GCC_GP3_CLK 98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define GCC_PCIE_0_AUX_CLK 99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define GCC_PCIE_0_PIPE_CLK 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define GCC_PCIE_1_AUX_CLK 101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define GCC_PCIE_1_PIPE_CLK 102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define GCC_PDM2_CLK 103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define GCC_SDCC1_APPS_CLK 104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define GCC_SDCC2_APPS_CLK 105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define GCC_SDCC3_APPS_CLK 106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define GCC_SDCC4_APPS_CLK 107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define GCC_SYS_NOC_UFS_AXI_CLK 108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define GCC_SYS_NOC_USB3_AXI_CLK 109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define GCC_TSIF_REF_CLK 110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define GCC_UFS_AXI_CLK 111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define GCC_UFS_RX_CFG_CLK 112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define GCC_UFS_TX_CFG_CLK 113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define GCC_USB30_MASTER_CLK 114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define GCC_USB30_MOCK_UTMI_CLK 115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define GCC_USB3_PHY_AUX_CLK 116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define GCC_USB_HS_SYSTEM_CLK 117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define GCC_SDCC1_AHB_CLK 118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define GCC_LPASS_Q6_AXI_CLK 119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define GCC_MSS_Q6_BIMC_AXI_CLK 120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define GCC_PCIE_0_CFG_AHB_CLK 121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define GCC_PCIE_0_MSTR_AXI_CLK 122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define GCC_PCIE_0_SLV_AXI_CLK 123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define GCC_PCIE_1_CFG_AHB_CLK 124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define GCC_PCIE_1_MSTR_AXI_CLK 125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define GCC_PCIE_1_SLV_AXI_CLK 126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define GCC_PDM_AHB_CLK 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define GCC_SDCC2_AHB_CLK 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define GCC_SDCC3_AHB_CLK 129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define GCC_SDCC4_AHB_CLK 130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define GCC_TSIF_AHB_CLK 131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define GCC_UFS_AHB_CLK 132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define GCC_UFS_RX_SYMBOL_0_CLK 133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define GCC_UFS_RX_SYMBOL_1_CLK 134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define GCC_UFS_TX_SYMBOL_0_CLK 135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define GCC_UFS_TX_SYMBOL_1_CLK 136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define GCC_USB2_HS_PHY_SLEEP_CLK 137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define GCC_USB30_SLEEP_CLK 138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define GCC_USB_HS_AHB_CLK 139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define GCC_USB_PHY_CFG_AHB2PHY_CLK 140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* GDSCs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define PCIE_GDSC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define PCIE_0_GDSC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define PCIE_1_GDSC 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define USB30_GDSC 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define UFS_GDSC 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* Resets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define USB3_PHY_RESET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define USB3PHY_PHY_RESET 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define PCIE_PHY_0_RESET 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define PCIE_PHY_1_RESET 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define QUSB2_PHY_RESET 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags