Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2013, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #ifndef _DT_BINDINGS_CLK_MSM_GCC_8960_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #define _DT_BINDINGS_CLK_MSM_GCC_8960_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #define AFAB_CLK_SRC				0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #define AFAB_CORE_CLK				1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define SFAB_MSS_Q6_SW_A_CLK			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define SFAB_MSS_Q6_FW_A_CLK			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define QDSS_STM_CLK				4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define SCSS_A_CLK				5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define SCSS_H_CLK				6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define SCSS_XO_SRC_CLK				7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define AFAB_EBI1_CH0_A_CLK			8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define AFAB_EBI1_CH1_A_CLK			9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define AFAB_AXI_S0_FCLK			10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define AFAB_AXI_S1_FCLK			11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define AFAB_AXI_S2_FCLK			12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define AFAB_AXI_S3_FCLK			13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define AFAB_AXI_S4_FCLK			14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define SFAB_CORE_CLK				15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define SFAB_AXI_S0_FCLK			16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define SFAB_AXI_S1_FCLK			17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define SFAB_AXI_S2_FCLK			18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define SFAB_AXI_S3_FCLK			19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define SFAB_AXI_S4_FCLK			20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define SFAB_AHB_S0_FCLK			21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define SFAB_AHB_S1_FCLK			22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define SFAB_AHB_S2_FCLK			23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define SFAB_AHB_S3_FCLK			24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define SFAB_AHB_S4_FCLK			25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define SFAB_AHB_S5_FCLK			26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define SFAB_AHB_S6_FCLK			27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define SFAB_AHB_S7_FCLK			28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define QDSS_AT_CLK_SRC				29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define QDSS_AT_CLK				30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define QDSS_TRACECLKIN_CLK_SRC			31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define QDSS_TRACECLKIN_CLK			32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define QDSS_TSCTR_CLK_SRC			33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define QDSS_TSCTR_CLK				34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define SFAB_ADM0_M0_A_CLK			35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define SFAB_ADM0_M1_A_CLK			36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define SFAB_ADM0_M2_H_CLK			37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define ADM0_CLK				38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define ADM0_PBUS_CLK				39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define MSS_XPU_CLK				40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define IMEM0_A_CLK				41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define QDSS_H_CLK				42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define PCIE_A_CLK				43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define PCIE_AUX_CLK				44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define PCIE_PHY_REF_CLK			45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define PCIE_H_CLK				46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define SFAB_CLK_SRC				47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define MAHB0_CLK				48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define Q6SW_CLK_SRC				49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define Q6SW_CLK				50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define Q6FW_CLK_SRC				51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define Q6FW_CLK				52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define SFAB_MSS_M_A_CLK			53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define SFAB_USB3_M_A_CLK			54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define SFAB_LPASS_Q6_A_CLK			55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define SFAB_AFAB_M_A_CLK			56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define AFAB_SFAB_M0_A_CLK			57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define AFAB_SFAB_M1_A_CLK			58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define SFAB_SATA_S_H_CLK			59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define DFAB_CLK_SRC				60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define DFAB_CLK				61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define SFAB_DFAB_M_A_CLK			62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define DFAB_SFAB_M_A_CLK			63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define DFAB_SWAY0_H_CLK			64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define DFAB_SWAY1_H_CLK			65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define DFAB_ARB0_H_CLK				66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define DFAB_ARB1_H_CLK				67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define PPSS_H_CLK				68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define PPSS_PROC_CLK				69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define PPSS_TIMER0_CLK				70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define PPSS_TIMER1_CLK				71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define PMEM_A_CLK				72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define DMA_BAM_H_CLK				73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define SIC_H_CLK				74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define SPS_TIC_H_CLK				75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define SLIMBUS_H_CLK				76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define SLIMBUS_XO_SRC_CLK			77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define CFPB_2X_CLK_SRC				78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define CFPB_CLK				79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define CFPB0_H_CLK				80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define CFPB1_H_CLK				81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define CFPB2_H_CLK				82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define SFAB_CFPB_M_H_CLK			83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define CFPB_MASTER_H_CLK			84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define SFAB_CFPB_S_H_CLK			85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define CFPB_SPLITTER_H_CLK			86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define TSIF_H_CLK				87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define TSIF_INACTIVITY_TIMERS_CLK		88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define TSIF_REF_SRC				89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define TSIF_REF_CLK				90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define CE1_H_CLK				91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define CE1_CORE_CLK				92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define CE1_SLEEP_CLK				93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define CE2_H_CLK				94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define CE2_CORE_CLK				95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SFPB_H_CLK_SRC				97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SFPB_H_CLK				98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SFAB_SFPB_M_H_CLK			99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define SFAB_SFPB_S_H_CLK			100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define RPM_PROC_CLK				101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define RPM_BUS_H_CLK				102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define RPM_SLEEP_CLK				103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define RPM_TIMER_CLK				104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define RPM_MSG_RAM_H_CLK			105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define PMIC_ARB0_H_CLK				106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define PMIC_ARB1_H_CLK				107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define PMIC_SSBI2_SRC				108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define PMIC_SSBI2_CLK				109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define SDC1_H_CLK				110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define SDC2_H_CLK				111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define SDC3_H_CLK				112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define SDC4_H_CLK				113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define SDC5_H_CLK				114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define SDC1_SRC				115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define SDC2_SRC				116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define SDC3_SRC				117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define SDC4_SRC				118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define SDC5_SRC				119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define SDC1_CLK				120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define SDC2_CLK				121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define SDC3_CLK				122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define SDC4_CLK				123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define SDC5_CLK				124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define DFAB_A2_H_CLK				125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define USB_HS1_H_CLK				126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define USB_HS1_XCVR_SRC			127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define USB_HS1_XCVR_CLK			128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define USB_HSIC_H_CLK				129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define USB_HSIC_XCVR_FS_SRC			130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define USB_HSIC_XCVR_FS_CLK			131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define USB_HSIC_SYSTEM_CLK_SRC			132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define USB_HSIC_SYSTEM_CLK			133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define CFPB0_C0_H_CLK				134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define CFPB0_C1_H_CLK				135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define CFPB0_D0_H_CLK				136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define CFPB0_D1_H_CLK				137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define USB_FS1_H_CLK				138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define USB_FS1_XCVR_FS_SRC			139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define USB_FS1_XCVR_FS_CLK			140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define USB_FS1_SYSTEM_CLK			141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define USB_FS2_H_CLK				142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define USB_FS2_XCVR_FS_SRC			143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define USB_FS2_XCVR_FS_CLK			144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define USB_FS2_SYSTEM_CLK			145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define GSBI_COMMON_SIM_SRC			146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define GSBI1_H_CLK				147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define GSBI2_H_CLK				148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define GSBI3_H_CLK				149
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define GSBI4_H_CLK				150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define GSBI5_H_CLK				151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define GSBI6_H_CLK				152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define GSBI7_H_CLK				153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define GSBI8_H_CLK				154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define GSBI9_H_CLK				155
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define GSBI10_H_CLK				156
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define GSBI11_H_CLK				157
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define GSBI12_H_CLK				158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define GSBI1_UART_SRC				159
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define GSBI1_UART_CLK				160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define GSBI2_UART_SRC				161
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define GSBI2_UART_CLK				162
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define GSBI3_UART_SRC				163
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define GSBI3_UART_CLK				164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define GSBI4_UART_SRC				165
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define GSBI4_UART_CLK				166
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define GSBI5_UART_SRC				167
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define GSBI5_UART_CLK				168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define GSBI6_UART_SRC				169
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define GSBI6_UART_CLK				170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define GSBI7_UART_SRC				171
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define GSBI7_UART_CLK				172
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define GSBI8_UART_SRC				173
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define GSBI8_UART_CLK				174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define GSBI9_UART_SRC				175
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define GSBI9_UART_CLK				176
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define GSBI10_UART_SRC				177
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define GSBI10_UART_CLK				178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define GSBI11_UART_SRC				179
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define GSBI11_UART_CLK				180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define GSBI12_UART_SRC				181
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define GSBI12_UART_CLK				182
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define GSBI1_QUP_SRC				183
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define GSBI1_QUP_CLK				184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define GSBI2_QUP_SRC				185
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define GSBI2_QUP_CLK				186
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define GSBI3_QUP_SRC				187
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define GSBI3_QUP_CLK				188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define GSBI4_QUP_SRC				189
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define GSBI4_QUP_CLK				190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define GSBI5_QUP_SRC				191
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define GSBI5_QUP_CLK				192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define GSBI6_QUP_SRC				193
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define GSBI6_QUP_CLK				194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define GSBI7_QUP_SRC				195
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define GSBI7_QUP_CLK				196
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define GSBI8_QUP_SRC				197
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define GSBI8_QUP_CLK				198
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define GSBI9_QUP_SRC				199
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define GSBI9_QUP_CLK				200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define GSBI10_QUP_SRC				201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define GSBI10_QUP_CLK				202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define GSBI11_QUP_SRC				203
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define GSBI11_QUP_CLK				204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define GSBI12_QUP_SRC				205
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define GSBI12_QUP_CLK				206
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define GSBI1_SIM_CLK				207
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define GSBI2_SIM_CLK				208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define GSBI3_SIM_CLK				209
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define GSBI4_SIM_CLK				210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define GSBI5_SIM_CLK				211
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define GSBI6_SIM_CLK				212
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define GSBI7_SIM_CLK				213
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define GSBI8_SIM_CLK				214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define GSBI9_SIM_CLK				215
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define GSBI10_SIM_CLK				216
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define GSBI11_SIM_CLK				217
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define GSBI12_SIM_CLK				218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define USB_HSIC_HSIC_CLK_SRC			219
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define USB_HSIC_HSIC_CLK			220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define USB_HSIC_HSIO_CAL_CLK			221
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define SPDM_CFG_H_CLK				222
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define SPDM_MSTR_H_CLK				223
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define SPDM_FF_CLK_SRC				224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define SPDM_FF_CLK				225
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define SEC_CTRL_CLK				226
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define SEC_CTRL_ACC_CLK_SRC			227
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define SEC_CTRL_ACC_CLK			228
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define TLMM_H_CLK				229
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define TLMM_CLK				230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define SFAB_MSS_S_H_CLK			231
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define MSS_SLP_CLK				232
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define MSS_Q6SW_JTAG_CLK			233
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define MSS_Q6FW_JTAG_CLK			234
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define MSS_S_H_CLK				235
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define MSS_CXO_SRC_CLK				236
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define SATA_H_CLK				237
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define SATA_CLK_SRC				238
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define SATA_RXOOB_CLK				239
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define SATA_PMALIVE_CLK			240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define SATA_PHY_REF_CLK			241
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define TSSC_CLK_SRC				242
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define TSSC_CLK				243
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define PDM_SRC					244
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define PDM_CLK					245
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define GP0_SRC					246
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define GP0_CLK					247
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define GP1_SRC					248
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define GP1_CLK					249
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define GP2_SRC					250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define GP2_CLK					251
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define MPM_CLK					252
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define EBI1_CLK_SRC				253
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define EBI1_CH0_CLK				254
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define EBI1_CH1_CLK				255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define EBI1_2X_CLK				256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define EBI1_CH0_DQ_CLK				257
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define EBI1_CH1_DQ_CLK				258
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define EBI1_CH0_CA_CLK				259
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define EBI1_CH1_CA_CLK				260
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define EBI1_XO_CLK				261
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define SFAB_SMPSS_S_H_CLK			262
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define PRNG_SRC				263
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define PRNG_CLK				264
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define PXO_SRC					265
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define LPASS_CXO_CLK				266
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define LPASS_PXO_CLK				267
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define SPDM_CY_PORT0_CLK			268
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define SPDM_CY_PORT1_CLK			269
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define SPDM_CY_PORT2_CLK			270
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define SPDM_CY_PORT3_CLK			271
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define SPDM_CY_PORT4_CLK			272
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define SPDM_CY_PORT5_CLK			273
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define SPDM_CY_PORT6_CLK			274
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define SPDM_CY_PORT7_CLK			275
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define PLL0					276
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define PLL0_VOTE				277
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define PLL3					278
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define PLL3_VOTE				279
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define PLL4_VOTE				280
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define PLL5					281
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define PLL5_VOTE				282
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define PLL6					283
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define PLL6_VOTE				284
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define PLL7_VOTE				285
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define PLL8					286
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define PLL8_VOTE				287
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define PLL9					288
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define PLL10					289
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define PLL11					290
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define PLL12					291
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define PLL13					292
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define PLL14					293
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define PLL14_VOTE				294
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define USB_HS3_H_CLK				295
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define USB_HS3_XCVR_SRC			296
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define USB_HS3_XCVR_CLK			297
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define USB_HS4_H_CLK				298
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define USB_HS4_XCVR_SRC			299
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define USB_HS4_XCVR_CLK			300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define SATA_PHY_CFG_CLK			301
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define SATA_A_CLK				302
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define CE3_SRC					303
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define CE3_CORE_CLK				304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define CE3_H_CLK				305
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define PLL16					306
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define PLL17					307
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #endif