^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2015 Linaro Limited
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef _DT_BINDINGS_CLK_MSM_GCC_8916_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define _DT_BINDINGS_CLK_MSM_GCC_8916_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define GPLL0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define GPLL0_VOTE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define BIMC_PLL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define BIMC_PLL_VOTE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define GPLL1 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define GPLL1_VOTE 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define GPLL2 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define GPLL2_VOTE 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define PCNOC_BFDCD_CLK_SRC 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SYSTEM_NOC_BFDCD_CLK_SRC 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CAMSS_AHB_CLK_SRC 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define APSS_AHB_CLK_SRC 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CSI0_CLK_SRC 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CSI1_CLK_SRC 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define GFX3D_CLK_SRC 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define VFE0_CLK_SRC 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define BLSP1_QUP1_I2C_APPS_CLK_SRC 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define BLSP1_QUP1_SPI_APPS_CLK_SRC 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define BLSP1_QUP2_I2C_APPS_CLK_SRC 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define BLSP1_QUP2_SPI_APPS_CLK_SRC 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define BLSP1_QUP3_I2C_APPS_CLK_SRC 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define BLSP1_QUP3_SPI_APPS_CLK_SRC 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define BLSP1_QUP4_I2C_APPS_CLK_SRC 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define BLSP1_QUP4_SPI_APPS_CLK_SRC 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define BLSP1_QUP5_I2C_APPS_CLK_SRC 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define BLSP1_QUP5_SPI_APPS_CLK_SRC 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define BLSP1_QUP6_I2C_APPS_CLK_SRC 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define BLSP1_QUP6_SPI_APPS_CLK_SRC 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define BLSP1_UART1_APPS_CLK_SRC 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define BLSP1_UART2_APPS_CLK_SRC 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CCI_CLK_SRC 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CAMSS_GP0_CLK_SRC 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CAMSS_GP1_CLK_SRC 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define JPEG0_CLK_SRC 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MCLK0_CLK_SRC 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MCLK1_CLK_SRC 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CSI0PHYTIMER_CLK_SRC 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CSI1PHYTIMER_CLK_SRC 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CPP_CLK_SRC 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CRYPTO_CLK_SRC 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define GP1_CLK_SRC 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define GP2_CLK_SRC 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define GP3_CLK_SRC 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define BYTE0_CLK_SRC 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define ESC0_CLK_SRC 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MDP_CLK_SRC 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PCLK0_CLK_SRC 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define VSYNC_CLK_SRC 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PDM2_CLK_SRC 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SDCC1_APPS_CLK_SRC 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SDCC2_APPS_CLK_SRC 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define APSS_TCU_CLK_SRC 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define USB_HS_SYSTEM_CLK_SRC 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define VCODEC0_CLK_SRC 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define GCC_BLSP1_AHB_CLK 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define GCC_BLSP1_SLEEP_CLK 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define GCC_BLSP1_QUP1_I2C_APPS_CLK 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define GCC_BLSP1_QUP1_SPI_APPS_CLK 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define GCC_BLSP1_QUP2_I2C_APPS_CLK 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define GCC_BLSP1_QUP2_SPI_APPS_CLK 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define GCC_BLSP1_QUP3_I2C_APPS_CLK 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define GCC_BLSP1_QUP3_SPI_APPS_CLK 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define GCC_BLSP1_QUP4_I2C_APPS_CLK 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define GCC_BLSP1_QUP4_SPI_APPS_CLK 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define GCC_BLSP1_QUP5_I2C_APPS_CLK 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define GCC_BLSP1_QUP5_SPI_APPS_CLK 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define GCC_BLSP1_QUP6_I2C_APPS_CLK 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define GCC_BLSP1_QUP6_SPI_APPS_CLK 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define GCC_BLSP1_UART1_APPS_CLK 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define GCC_BLSP1_UART2_APPS_CLK 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define GCC_BOOT_ROM_AHB_CLK 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define GCC_CAMSS_CCI_AHB_CLK 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define GCC_CAMSS_CCI_CLK 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define GCC_CAMSS_CSI0_AHB_CLK 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define GCC_CAMSS_CSI0_CLK 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define GCC_CAMSS_CSI0PHY_CLK 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define GCC_CAMSS_CSI0PIX_CLK 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define GCC_CAMSS_CSI0RDI_CLK 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define GCC_CAMSS_CSI1_AHB_CLK 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define GCC_CAMSS_CSI1_CLK 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define GCC_CAMSS_CSI1PHY_CLK 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define GCC_CAMSS_CSI1PIX_CLK 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define GCC_CAMSS_CSI1RDI_CLK 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define GCC_CAMSS_CSI_VFE0_CLK 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define GCC_CAMSS_GP0_CLK 84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define GCC_CAMSS_GP1_CLK 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define GCC_CAMSS_ISPIF_AHB_CLK 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define GCC_CAMSS_JPEG0_CLK 87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define GCC_CAMSS_JPEG_AHB_CLK 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define GCC_CAMSS_JPEG_AXI_CLK 89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define GCC_CAMSS_MCLK0_CLK 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define GCC_CAMSS_MCLK1_CLK 91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define GCC_CAMSS_MICRO_AHB_CLK 92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define GCC_CAMSS_CSI0PHYTIMER_CLK 93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define GCC_CAMSS_CSI1PHYTIMER_CLK 94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define GCC_CAMSS_AHB_CLK 95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define GCC_CAMSS_TOP_AHB_CLK 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define GCC_CAMSS_CPP_AHB_CLK 97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define GCC_CAMSS_CPP_CLK 98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define GCC_CAMSS_VFE0_CLK 99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define GCC_CAMSS_VFE_AHB_CLK 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define GCC_CAMSS_VFE_AXI_CLK 101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define GCC_CRYPTO_AHB_CLK 102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define GCC_CRYPTO_AXI_CLK 103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define GCC_CRYPTO_CLK 104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define GCC_OXILI_GMEM_CLK 105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define GCC_GP1_CLK 106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define GCC_GP2_CLK 107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define GCC_GP3_CLK 108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define GCC_MDSS_AHB_CLK 109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define GCC_MDSS_AXI_CLK 110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define GCC_MDSS_BYTE0_CLK 111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define GCC_MDSS_ESC0_CLK 112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define GCC_MDSS_MDP_CLK 113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define GCC_MDSS_PCLK0_CLK 114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define GCC_MDSS_VSYNC_CLK 115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define GCC_MSS_CFG_AHB_CLK 116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define GCC_OXILI_AHB_CLK 117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define GCC_OXILI_GFX3D_CLK 118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define GCC_PDM2_CLK 119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define GCC_PDM_AHB_CLK 120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define GCC_PRNG_AHB_CLK 121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define GCC_SDCC1_AHB_CLK 122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define GCC_SDCC1_APPS_CLK 123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define GCC_SDCC2_AHB_CLK 124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define GCC_SDCC2_APPS_CLK 125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define GCC_GTCU_AHB_CLK 126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define GCC_JPEG_TBU_CLK 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define GCC_MDP_TBU_CLK 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define GCC_SMMU_CFG_CLK 129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define GCC_VENUS_TBU_CLK 130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define GCC_VFE_TBU_CLK 131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define GCC_USB2A_PHY_SLEEP_CLK 132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define GCC_USB_HS_AHB_CLK 133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define GCC_USB_HS_SYSTEM_CLK 134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define GCC_VENUS0_AHB_CLK 135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define GCC_VENUS0_AXI_CLK 136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define GCC_VENUS0_VCODEC0_CLK 137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define BIMC_DDR_CLK_SRC 138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define GCC_APSS_TCU_CLK 139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define GCC_GFX_TCU_CLK 140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define BIMC_GPU_CLK_SRC 141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define GCC_BIMC_GFX_CLK 142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define GCC_BIMC_GPU_CLK 143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define ULTAUDIO_LPAIF_PRI_I2S_CLK_SRC 144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define ULTAUDIO_LPAIF_SEC_I2S_CLK_SRC 145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define ULTAUDIO_LPAIF_AUX_I2S_CLK_SRC 146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define ULTAUDIO_XO_CLK_SRC 147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define ULTAUDIO_AHBFABRIC_CLK_SRC 148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define CODEC_DIGCODEC_CLK_SRC 149
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define GCC_ULTAUDIO_PCNOC_MPORT_CLK 150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define GCC_ULTAUDIO_PCNOC_SWAY_CLK 151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define GCC_ULTAUDIO_AVSYNC_XO_CLK 152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define GCC_ULTAUDIO_STC_XO_CLK 153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK 154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CLK 155
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK 156
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK 157
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK 158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define GCC_CODEC_DIGCODEC_CLK 159
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define GCC_MSS_Q6_BIMC_AXI_CLK 160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* Indexes for GDSCs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define BIMC_GDSC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define VENUS_GDSC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define MDSS_GDSC 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define JPEG_GDSC 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define VFE_GDSC 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define OXILI_GDSC 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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