^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_8074_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define _DT_BINDINGS_CLOCK_IPQ_GCC_8074_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define GPLL0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define GPLL0_MAIN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define GCC_SLEEP_CLK_SRC 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define BLSP1_QUP1_I2C_APPS_CLK_SRC 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define BLSP1_QUP1_SPI_APPS_CLK_SRC 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define BLSP1_QUP2_I2C_APPS_CLK_SRC 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define BLSP1_QUP2_SPI_APPS_CLK_SRC 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define BLSP1_QUP3_I2C_APPS_CLK_SRC 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define BLSP1_QUP3_SPI_APPS_CLK_SRC 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define BLSP1_QUP4_I2C_APPS_CLK_SRC 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define BLSP1_QUP4_SPI_APPS_CLK_SRC 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define BLSP1_QUP5_I2C_APPS_CLK_SRC 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define BLSP1_QUP5_SPI_APPS_CLK_SRC 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define BLSP1_QUP6_I2C_APPS_CLK_SRC 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define BLSP1_QUP6_SPI_APPS_CLK_SRC 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define BLSP1_UART1_APPS_CLK_SRC 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define BLSP1_UART2_APPS_CLK_SRC 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define BLSP1_UART3_APPS_CLK_SRC 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define BLSP1_UART4_APPS_CLK_SRC 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define BLSP1_UART5_APPS_CLK_SRC 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define BLSP1_UART6_APPS_CLK_SRC 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define GCC_BLSP1_AHB_CLK 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define GCC_BLSP1_QUP1_I2C_APPS_CLK 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define GCC_BLSP1_QUP1_SPI_APPS_CLK 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define GCC_BLSP1_QUP2_I2C_APPS_CLK 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define GCC_BLSP1_QUP2_SPI_APPS_CLK 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define GCC_BLSP1_QUP3_I2C_APPS_CLK 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define GCC_BLSP1_QUP3_SPI_APPS_CLK 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define GCC_BLSP1_QUP4_I2C_APPS_CLK 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define GCC_BLSP1_QUP4_SPI_APPS_CLK 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define GCC_BLSP1_QUP5_I2C_APPS_CLK 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define GCC_BLSP1_QUP5_SPI_APPS_CLK 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define GCC_BLSP1_QUP6_I2C_APPS_CLK 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define GCC_BLSP1_QUP6_SPI_APPS_CLK 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define GCC_BLSP1_UART1_APPS_CLK 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define GCC_BLSP1_UART2_APPS_CLK 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define GCC_BLSP1_UART3_APPS_CLK 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define GCC_BLSP1_UART4_APPS_CLK 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define GCC_BLSP1_UART5_APPS_CLK 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define GCC_BLSP1_UART6_APPS_CLK 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define GCC_PRNG_AHB_CLK 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define GCC_QPIC_AHB_CLK 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define GCC_QPIC_CLK 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PCNOC_BFDCD_CLK_SRC 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define GPLL2_MAIN 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define GPLL2 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define GPLL4_MAIN 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define GPLL4 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define GPLL6_MAIN 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define GPLL6 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define UBI32_PLL_MAIN 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define UBI32_PLL 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define NSS_CRYPTO_PLL_MAIN 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define NSS_CRYPTO_PLL 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define PCIE0_AXI_CLK_SRC 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define PCIE0_AUX_CLK_SRC 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define PCIE0_PIPE_CLK_SRC 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define PCIE1_AXI_CLK_SRC 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define PCIE1_AUX_CLK_SRC 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PCIE1_PIPE_CLK_SRC 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SDCC1_APPS_CLK_SRC 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SDCC1_ICE_CORE_CLK_SRC 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SDCC2_APPS_CLK_SRC 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define USB0_MASTER_CLK_SRC 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define USB0_AUX_CLK_SRC 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define USB0_MOCK_UTMI_CLK_SRC 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define USB0_PIPE_CLK_SRC 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define USB1_MASTER_CLK_SRC 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define USB1_AUX_CLK_SRC 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define USB1_MOCK_UTMI_CLK_SRC 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define USB1_PIPE_CLK_SRC 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define GCC_XO_CLK_SRC 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SYSTEM_NOC_BFDCD_CLK_SRC 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define NSS_CE_CLK_SRC 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define NSS_NOC_BFDCD_CLK_SRC 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define NSS_CRYPTO_CLK_SRC 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define NSS_UBI0_CLK_SRC 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define NSS_UBI0_DIV_CLK_SRC 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define NSS_UBI1_CLK_SRC 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define NSS_UBI1_DIV_CLK_SRC 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define UBI_MPT_CLK_SRC 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define NSS_IMEM_CLK_SRC 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define NSS_PPE_CLK_SRC 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define NSS_PORT1_RX_CLK_SRC 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define NSS_PORT1_RX_DIV_CLK_SRC 84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define NSS_PORT1_TX_CLK_SRC 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define NSS_PORT1_TX_DIV_CLK_SRC 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define NSS_PORT2_RX_CLK_SRC 87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define NSS_PORT2_RX_DIV_CLK_SRC 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define NSS_PORT2_TX_CLK_SRC 89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define NSS_PORT2_TX_DIV_CLK_SRC 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define NSS_PORT3_RX_CLK_SRC 91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define NSS_PORT3_RX_DIV_CLK_SRC 92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define NSS_PORT3_TX_CLK_SRC 93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define NSS_PORT3_TX_DIV_CLK_SRC 94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define NSS_PORT4_RX_CLK_SRC 95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define NSS_PORT4_RX_DIV_CLK_SRC 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define NSS_PORT4_TX_CLK_SRC 97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define NSS_PORT4_TX_DIV_CLK_SRC 98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define NSS_PORT5_RX_CLK_SRC 99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define NSS_PORT5_RX_DIV_CLK_SRC 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define NSS_PORT5_TX_CLK_SRC 101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define NSS_PORT5_TX_DIV_CLK_SRC 102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define NSS_PORT6_RX_CLK_SRC 103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define NSS_PORT6_RX_DIV_CLK_SRC 104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define NSS_PORT6_TX_CLK_SRC 105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define NSS_PORT6_TX_DIV_CLK_SRC 106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define CRYPTO_CLK_SRC 107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define GP1_CLK_SRC 108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define GP2_CLK_SRC 109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define GP3_CLK_SRC 110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define GCC_PCIE0_AHB_CLK 111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define GCC_PCIE0_AUX_CLK 112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define GCC_PCIE0_AXI_M_CLK 113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define GCC_PCIE0_AXI_S_CLK 114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define GCC_PCIE0_PIPE_CLK 115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define GCC_SYS_NOC_PCIE0_AXI_CLK 116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define GCC_PCIE1_AHB_CLK 117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define GCC_PCIE1_AUX_CLK 118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define GCC_PCIE1_AXI_M_CLK 119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define GCC_PCIE1_AXI_S_CLK 120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define GCC_PCIE1_PIPE_CLK 121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define GCC_SYS_NOC_PCIE1_AXI_CLK 122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define GCC_USB0_AUX_CLK 123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define GCC_SYS_NOC_USB0_AXI_CLK 124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define GCC_USB0_MASTER_CLK 125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define GCC_USB0_MOCK_UTMI_CLK 126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define GCC_USB0_PHY_CFG_AHB_CLK 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define GCC_USB0_PIPE_CLK 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define GCC_USB0_SLEEP_CLK 129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define GCC_USB1_AUX_CLK 130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define GCC_SYS_NOC_USB1_AXI_CLK 131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define GCC_USB1_MASTER_CLK 132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define GCC_USB1_MOCK_UTMI_CLK 133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define GCC_USB1_PHY_CFG_AHB_CLK 134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define GCC_USB1_PIPE_CLK 135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define GCC_USB1_SLEEP_CLK 136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define GCC_SDCC1_AHB_CLK 137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define GCC_SDCC1_APPS_CLK 138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define GCC_SDCC1_ICE_CORE_CLK 139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define GCC_SDCC2_AHB_CLK 140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define GCC_SDCC2_APPS_CLK 141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define GCC_MEM_NOC_NSS_AXI_CLK 142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define GCC_NSS_CE_APB_CLK 143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define GCC_NSS_CE_AXI_CLK 144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define GCC_NSS_CFG_CLK 145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define GCC_NSS_CRYPTO_CLK 146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define GCC_NSS_CSR_CLK 147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define GCC_NSS_EDMA_CFG_CLK 148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define GCC_NSS_EDMA_CLK 149
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define GCC_NSS_IMEM_CLK 150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define GCC_NSS_NOC_CLK 151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define GCC_NSS_PPE_BTQ_CLK 152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define GCC_NSS_PPE_CFG_CLK 153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define GCC_NSS_PPE_CLK 154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define GCC_NSS_PPE_IPE_CLK 155
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define GCC_NSS_PTP_REF_CLK 156
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define GCC_NSSNOC_CE_APB_CLK 157
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define GCC_NSSNOC_CE_AXI_CLK 158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define GCC_NSSNOC_CRYPTO_CLK 159
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define GCC_NSSNOC_PPE_CFG_CLK 160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define GCC_NSSNOC_PPE_CLK 161
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define GCC_NSSNOC_QOSGEN_REF_CLK 162
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define GCC_NSSNOC_SNOC_CLK 163
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define GCC_NSSNOC_TIMEOUT_REF_CLK 164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define GCC_NSSNOC_UBI0_AHB_CLK 165
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define GCC_NSSNOC_UBI1_AHB_CLK 166
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define GCC_UBI0_AHB_CLK 167
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define GCC_UBI0_AXI_CLK 168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define GCC_UBI0_NC_AXI_CLK 169
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define GCC_UBI0_CORE_CLK 170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define GCC_UBI0_MPT_CLK 171
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define GCC_UBI1_AHB_CLK 172
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define GCC_UBI1_AXI_CLK 173
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define GCC_UBI1_NC_AXI_CLK 174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define GCC_UBI1_CORE_CLK 175
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define GCC_UBI1_MPT_CLK 176
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define GCC_CMN_12GPLL_AHB_CLK 177
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define GCC_CMN_12GPLL_SYS_CLK 178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define GCC_MDIO_AHB_CLK 179
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define GCC_UNIPHY0_AHB_CLK 180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define GCC_UNIPHY0_SYS_CLK 181
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define GCC_UNIPHY1_AHB_CLK 182
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define GCC_UNIPHY1_SYS_CLK 183
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define GCC_UNIPHY2_AHB_CLK 184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define GCC_UNIPHY2_SYS_CLK 185
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define GCC_NSS_PORT1_RX_CLK 186
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define GCC_NSS_PORT1_TX_CLK 187
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define GCC_NSS_PORT2_RX_CLK 188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define GCC_NSS_PORT2_TX_CLK 189
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define GCC_NSS_PORT3_RX_CLK 190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define GCC_NSS_PORT3_TX_CLK 191
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define GCC_NSS_PORT4_RX_CLK 192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define GCC_NSS_PORT4_TX_CLK 193
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define GCC_NSS_PORT5_RX_CLK 194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define GCC_NSS_PORT5_TX_CLK 195
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define GCC_NSS_PORT6_RX_CLK 196
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define GCC_NSS_PORT6_TX_CLK 197
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define GCC_PORT1_MAC_CLK 198
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define GCC_PORT2_MAC_CLK 199
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define GCC_PORT3_MAC_CLK 200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define GCC_PORT4_MAC_CLK 201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define GCC_PORT5_MAC_CLK 202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define GCC_PORT6_MAC_CLK 203
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define GCC_UNIPHY0_PORT1_RX_CLK 204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define GCC_UNIPHY0_PORT1_TX_CLK 205
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define GCC_UNIPHY0_PORT2_RX_CLK 206
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define GCC_UNIPHY0_PORT2_TX_CLK 207
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define GCC_UNIPHY0_PORT3_RX_CLK 208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define GCC_UNIPHY0_PORT3_TX_CLK 209
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define GCC_UNIPHY0_PORT4_RX_CLK 210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define GCC_UNIPHY0_PORT4_TX_CLK 211
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define GCC_UNIPHY0_PORT5_RX_CLK 212
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define GCC_UNIPHY0_PORT5_TX_CLK 213
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define GCC_UNIPHY1_PORT5_RX_CLK 214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define GCC_UNIPHY1_PORT5_TX_CLK 215
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define GCC_UNIPHY2_PORT6_RX_CLK 216
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define GCC_UNIPHY2_PORT6_TX_CLK 217
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define GCC_CRYPTO_AHB_CLK 218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define GCC_CRYPTO_AXI_CLK 219
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define GCC_CRYPTO_CLK 220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define GCC_GP1_CLK 221
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define GCC_GP2_CLK 222
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define GCC_GP3_CLK 223
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define GCC_PCIE0_AXI_S_BRIDGE_CLK 224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define GCC_PCIE0_RCHNG_CLK_SRC 225
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define GCC_PCIE0_RCHNG_CLK 226
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define GCC_BLSP1_BCR 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define GCC_BLSP1_QUP1_BCR 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define GCC_BLSP1_UART1_BCR 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define GCC_BLSP1_QUP2_BCR 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define GCC_BLSP1_UART2_BCR 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define GCC_BLSP1_QUP3_BCR 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define GCC_BLSP1_UART3_BCR 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define GCC_BLSP1_QUP4_BCR 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define GCC_BLSP1_UART4_BCR 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define GCC_BLSP1_QUP5_BCR 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define GCC_BLSP1_UART5_BCR 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define GCC_BLSP1_QUP6_BCR 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define GCC_BLSP1_UART6_BCR 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define GCC_IMEM_BCR 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define GCC_SMMU_BCR 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define GCC_APSS_TCU_BCR 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define GCC_SMMU_XPU_BCR 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define GCC_PCNOC_TBU_BCR 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define GCC_SMMU_CFG_BCR 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define GCC_PRNG_BCR 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define GCC_BOOT_ROM_BCR 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define GCC_CRYPTO_BCR 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define GCC_WCSS_BCR 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define GCC_WCSS_Q6_BCR 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define GCC_NSS_BCR 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define GCC_SEC_CTRL_BCR 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define GCC_ADSS_BCR 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define GCC_DDRSS_BCR 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define GCC_SYSTEM_NOC_BCR 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define GCC_PCNOC_BCR 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define GCC_TCSR_BCR 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define GCC_QDSS_BCR 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define GCC_DCD_BCR 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define GCC_MSG_RAM_BCR 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define GCC_MPM_BCR 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define GCC_SPMI_BCR 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define GCC_SPDM_BCR 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define GCC_RBCPR_BCR 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define GCC_RBCPR_MX_BCR 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define GCC_TLMM_BCR 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define GCC_RBCPR_WCSS_BCR 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define GCC_USB0_PHY_BCR 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define GCC_USB3PHY_0_PHY_BCR 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define GCC_USB0_BCR 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define GCC_USB1_PHY_BCR 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define GCC_USB3PHY_1_PHY_BCR 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define GCC_USB1_BCR 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define GCC_QUSB2_0_PHY_BCR 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define GCC_QUSB2_1_PHY_BCR 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define GCC_SDCC1_BCR 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define GCC_SDCC2_BCR 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define GCC_SNOC_BUS_TIMEOUT0_BCR 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define GCC_SNOC_BUS_TIMEOUT2_BCR 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define GCC_SNOC_BUS_TIMEOUT3_BCR 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define GCC_PCNOC_BUS_TIMEOUT0_BCR 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define GCC_PCNOC_BUS_TIMEOUT1_BCR 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define GCC_PCNOC_BUS_TIMEOUT2_BCR 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define GCC_PCNOC_BUS_TIMEOUT3_BCR 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define GCC_PCNOC_BUS_TIMEOUT4_BCR 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define GCC_PCNOC_BUS_TIMEOUT5_BCR 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define GCC_PCNOC_BUS_TIMEOUT6_BCR 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define GCC_PCNOC_BUS_TIMEOUT7_BCR 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define GCC_PCNOC_BUS_TIMEOUT8_BCR 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define GCC_PCNOC_BUS_TIMEOUT9_BCR 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define GCC_UNIPHY0_BCR 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define GCC_UNIPHY1_BCR 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define GCC_UNIPHY2_BCR 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define GCC_CMN_12GPLL_BCR 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define GCC_QPIC_BCR 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define GCC_MDIO_BCR 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define GCC_PCIE1_TBU_BCR 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define GCC_WCSS_CORE_TBU_BCR 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define GCC_WCSS_Q6_TBU_BCR 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define GCC_USB0_TBU_BCR 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define GCC_USB1_TBU_BCR 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define GCC_PCIE0_TBU_BCR 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define GCC_NSS_NOC_TBU_BCR 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define GCC_PCIE0_BCR 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define GCC_PCIE0_PHY_BCR 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define GCC_PCIE0PHY_PHY_BCR 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define GCC_PCIE0_LINK_DOWN_BCR 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define GCC_PCIE1_BCR 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define GCC_PCIE1_PHY_BCR 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define GCC_PCIE1PHY_PHY_BCR 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define GCC_PCIE1_LINK_DOWN_BCR 84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define GCC_DCC_BCR 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define GCC_APC1_VOLTAGE_DROOP_DETECTOR_BCR 87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define GCC_SMMU_CATS_BCR 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define GCC_UBI0_AXI_ARES 89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define GCC_UBI0_AHB_ARES 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define GCC_UBI0_NC_AXI_ARES 91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define GCC_UBI0_DBG_ARES 92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define GCC_UBI0_CORE_CLAMP_ENABLE 93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define GCC_UBI0_CLKRST_CLAMP_ENABLE 94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define GCC_UBI1_AXI_ARES 95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define GCC_UBI1_AHB_ARES 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define GCC_UBI1_NC_AXI_ARES 97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define GCC_UBI1_DBG_ARES 98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define GCC_UBI1_CORE_CLAMP_ENABLE 99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define GCC_UBI1_CLKRST_CLAMP_ENABLE 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define GCC_NSS_CFG_ARES 101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define GCC_NSS_IMEM_ARES 102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define GCC_NSS_NOC_ARES 103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define GCC_NSS_CRYPTO_ARES 104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define GCC_NSS_CSR_ARES 105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define GCC_NSS_CE_APB_ARES 106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define GCC_NSS_CE_AXI_ARES 107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define GCC_NSSNOC_CE_APB_ARES 108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define GCC_NSSNOC_CE_AXI_ARES 109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define GCC_NSSNOC_UBI0_AHB_ARES 110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define GCC_NSSNOC_UBI1_AHB_ARES 111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define GCC_NSSNOC_SNOC_ARES 112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define GCC_NSSNOC_CRYPTO_ARES 113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define GCC_NSSNOC_ATB_ARES 114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define GCC_NSSNOC_QOSGEN_REF_ARES 115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define GCC_NSSNOC_TIMEOUT_REF_ARES 116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define GCC_PCIE0_PIPE_ARES 117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define GCC_PCIE0_SLEEP_ARES 118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define GCC_PCIE0_CORE_STICKY_ARES 119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define GCC_PCIE0_AXI_MASTER_ARES 120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define GCC_PCIE0_AXI_SLAVE_ARES 121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define GCC_PCIE0_AHB_ARES 122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define GCC_PCIE0_AXI_MASTER_STICKY_ARES 123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define GCC_PCIE1_PIPE_ARES 124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define GCC_PCIE1_SLEEP_ARES 125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define GCC_PCIE1_CORE_STICKY_ARES 126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define GCC_PCIE1_AXI_MASTER_ARES 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define GCC_PCIE1_AXI_SLAVE_ARES 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define GCC_PCIE1_AHB_ARES 129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define GCC_PCIE1_AXI_MASTER_STICKY_ARES 130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define GCC_PCIE0_AXI_SLAVE_STICKY_ARES 131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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