Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2014, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #ifndef _DT_BINDINGS_CLK_GCC_IPQ806X_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #define _DT_BINDINGS_CLK_GCC_IPQ806X_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #define AFAB_CLK_SRC				0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #define QDSS_STM_CLK				1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define SCSS_A_CLK				2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define SCSS_H_CLK				3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define AFAB_CORE_CLK				4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define SCSS_XO_SRC_CLK				5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define AFAB_EBI1_CH0_A_CLK			6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define AFAB_EBI1_CH1_A_CLK			7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define AFAB_AXI_S0_FCLK			8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define AFAB_AXI_S1_FCLK			9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define AFAB_AXI_S2_FCLK			10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define AFAB_AXI_S3_FCLK			11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define AFAB_AXI_S4_FCLK			12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define SFAB_CORE_CLK				13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define SFAB_AXI_S0_FCLK			14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define SFAB_AXI_S1_FCLK			15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define SFAB_AXI_S2_FCLK			16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define SFAB_AXI_S3_FCLK			17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define SFAB_AXI_S4_FCLK			18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define SFAB_AXI_S5_FCLK			19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define SFAB_AHB_S0_FCLK			20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define SFAB_AHB_S1_FCLK			21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define SFAB_AHB_S2_FCLK			22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define SFAB_AHB_S3_FCLK			23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define SFAB_AHB_S4_FCLK			24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define SFAB_AHB_S5_FCLK			25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define SFAB_AHB_S6_FCLK			26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define SFAB_AHB_S7_FCLK			27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define QDSS_AT_CLK_SRC				28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define QDSS_AT_CLK				29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define QDSS_TRACECLKIN_CLK_SRC			30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define QDSS_TRACECLKIN_CLK			31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define QDSS_TSCTR_CLK_SRC			32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define QDSS_TSCTR_CLK				33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define SFAB_ADM0_M0_A_CLK			34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define SFAB_ADM0_M1_A_CLK			35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define SFAB_ADM0_M2_H_CLK			36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define ADM0_CLK				37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define ADM0_PBUS_CLK				38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define IMEM0_A_CLK				39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define QDSS_H_CLK				40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define PCIE_A_CLK				41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define PCIE_AUX_CLK				42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define PCIE_H_CLK				43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define PCIE_PHY_CLK				44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define SFAB_CLK_SRC				45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define SFAB_LPASS_Q6_A_CLK			46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define SFAB_AFAB_M_A_CLK			47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define AFAB_SFAB_M0_A_CLK			48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define AFAB_SFAB_M1_A_CLK			49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define SFAB_SATA_S_H_CLK			50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define DFAB_CLK_SRC				51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define DFAB_CLK				52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define SFAB_DFAB_M_A_CLK			53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define DFAB_SFAB_M_A_CLK			54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define DFAB_SWAY0_H_CLK			55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define DFAB_SWAY1_H_CLK			56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define DFAB_ARB0_H_CLK				57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define DFAB_ARB1_H_CLK				58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define PPSS_H_CLK				59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define PPSS_PROC_CLK				60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define PPSS_TIMER0_CLK				61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define PPSS_TIMER1_CLK				62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define PMEM_A_CLK				63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define DMA_BAM_H_CLK				64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define SIC_H_CLK				65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define SPS_TIC_H_CLK				66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define CFPB_2X_CLK_SRC				67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define CFPB_CLK				68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define CFPB0_H_CLK				69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define CFPB1_H_CLK				70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define CFPB2_H_CLK				71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define SFAB_CFPB_M_H_CLK			72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define CFPB_MASTER_H_CLK			73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define SFAB_CFPB_S_H_CLK			74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define CFPB_SPLITTER_H_CLK			75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define TSIF_H_CLK				76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define TSIF_INACTIVITY_TIMERS_CLK		77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define TSIF_REF_SRC				78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define TSIF_REF_CLK				79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define CE1_H_CLK				80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define CE1_CORE_CLK				81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define CE1_SLEEP_CLK				82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define CE2_H_CLK				83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define CE2_CORE_CLK				84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define SFPB_H_CLK_SRC				85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define SFPB_H_CLK				86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define SFAB_SFPB_M_H_CLK			87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define SFAB_SFPB_S_H_CLK			88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define RPM_PROC_CLK				89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define RPM_BUS_H_CLK				90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define RPM_SLEEP_CLK				91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define RPM_TIMER_CLK				92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define RPM_MSG_RAM_H_CLK			93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define PMIC_ARB0_H_CLK				94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define PMIC_ARB1_H_CLK				95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define PMIC_SSBI2_SRC				96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define PMIC_SSBI2_CLK				97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SDC1_H_CLK				98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define SDC2_H_CLK				99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SDC3_H_CLK				100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define SDC4_H_CLK				101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define SDC1_SRC				102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define SDC1_CLK				103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define SDC2_SRC				104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SDC2_CLK				105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define SDC3_SRC				106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define SDC3_CLK				107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define SDC4_SRC				108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define SDC4_CLK				109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define USB_HS1_H_CLK				110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define USB_HS1_XCVR_SRC			111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define USB_HS1_XCVR_CLK			112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define USB_HSIC_H_CLK				113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define USB_HSIC_XCVR_SRC			114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define USB_HSIC_XCVR_CLK			115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define USB_HSIC_SYSTEM_CLK_SRC			116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define USB_HSIC_SYSTEM_CLK			117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define CFPB0_C0_H_CLK				118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define CFPB0_D0_H_CLK				119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define CFPB0_C1_H_CLK				120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define CFPB0_D1_H_CLK				121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define USB_FS1_H_CLK				122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define USB_FS1_XCVR_SRC			123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define USB_FS1_XCVR_CLK			124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define USB_FS1_SYSTEM_CLK			125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define GSBI_COMMON_SIM_SRC			126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define GSBI1_H_CLK				127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define GSBI2_H_CLK				128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define GSBI3_H_CLK				129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define GSBI4_H_CLK				130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define GSBI5_H_CLK				131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define GSBI6_H_CLK				132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define GSBI7_H_CLK				133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define GSBI1_QUP_SRC				134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define GSBI1_QUP_CLK				135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define GSBI2_QUP_SRC				136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define GSBI2_QUP_CLK				137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define GSBI3_QUP_SRC				138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define GSBI3_QUP_CLK				139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define GSBI4_QUP_SRC				140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define GSBI4_QUP_CLK				141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define GSBI5_QUP_SRC				142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define GSBI5_QUP_CLK				143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define GSBI6_QUP_SRC				144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define GSBI6_QUP_CLK				145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define GSBI7_QUP_SRC				146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define GSBI7_QUP_CLK				147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define GSBI1_UART_SRC				148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define GSBI1_UART_CLK				149
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define GSBI2_UART_SRC				150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define GSBI2_UART_CLK				151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define GSBI3_UART_SRC				152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define GSBI3_UART_CLK				153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define GSBI4_UART_SRC				154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define GSBI4_UART_CLK				155
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define GSBI5_UART_SRC				156
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define GSBI5_UART_CLK				157
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define GSBI6_UART_SRC				158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define GSBI6_UART_CLK				159
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define GSBI7_UART_SRC				160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define GSBI7_UART_CLK				161
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define GSBI1_SIM_CLK				162
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define GSBI2_SIM_CLK				163
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define GSBI3_SIM_CLK				164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define GSBI4_SIM_CLK				165
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define GSBI5_SIM_CLK				166
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define GSBI6_SIM_CLK				167
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define GSBI7_SIM_CLK				168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define USB_HSIC_HSIC_CLK_SRC			169
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define USB_HSIC_HSIC_CLK			170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define USB_HSIC_HSIO_CAL_CLK			171
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define SPDM_CFG_H_CLK				172
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define SPDM_MSTR_H_CLK				173
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define SPDM_FF_CLK_SRC				174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define SPDM_FF_CLK				175
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define SEC_CTRL_CLK				176
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define SEC_CTRL_ACC_CLK_SRC			177
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define SEC_CTRL_ACC_CLK			178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define TLMM_H_CLK				179
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define TLMM_CLK				180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define SATA_H_CLK				181
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define SATA_CLK_SRC				182
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define SATA_RXOOB_CLK				183
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define SATA_PMALIVE_CLK			184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define SATA_PHY_REF_CLK			185
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define SATA_A_CLK				186
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define SATA_PHY_CFG_CLK			187
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define TSSC_CLK_SRC				188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define TSSC_CLK				189
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define PDM_SRC					190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define PDM_CLK					191
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define GP0_SRC					192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define GP0_CLK					193
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define GP1_SRC					194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define GP1_CLK					195
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define GP2_SRC					196
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define GP2_CLK					197
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define MPM_CLK					198
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define EBI1_CLK_SRC				199
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define EBI1_CH0_CLK				200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define EBI1_CH1_CLK				201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define EBI1_2X_CLK				202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define EBI1_CH0_DQ_CLK				203
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define EBI1_CH1_DQ_CLK				204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define EBI1_CH0_CA_CLK				205
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define EBI1_CH1_CA_CLK				206
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define EBI1_XO_CLK				207
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define SFAB_SMPSS_S_H_CLK			208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define PRNG_SRC				209
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define PRNG_CLK				210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define PXO_SRC					211
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define SPDM_CY_PORT0_CLK			212
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define SPDM_CY_PORT1_CLK			213
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define SPDM_CY_PORT2_CLK			214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define SPDM_CY_PORT3_CLK			215
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define SPDM_CY_PORT4_CLK			216
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define SPDM_CY_PORT5_CLK			217
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define SPDM_CY_PORT6_CLK			218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define SPDM_CY_PORT7_CLK			219
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define PLL0					220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define PLL0_VOTE				221
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define PLL3					222
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define PLL3_VOTE				223
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define PLL4_VOTE				225
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define PLL8					226
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define PLL8_VOTE				227
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define PLL9					228
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define PLL10					229
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define PLL11					230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define PLL12					231
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define PLL14					232
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define PLL14_VOTE				233
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define PLL18					234
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define CE5_SRC					235
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define CE5_H_CLK				236
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define CE5_CORE_CLK				237
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define CE3_SLEEP_CLK				238
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define SFAB_AHB_S8_FCLK			239
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define SPDM_CY_PORT8_CLK			246
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define PCIE_ALT_REF_SRC			247
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define PCIE_ALT_REF_CLK			248
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define PCIE_1_A_CLK				249
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define PCIE_1_AUX_CLK				250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define PCIE_1_H_CLK				251
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define PCIE_1_PHY_CLK				252
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define PCIE_1_ALT_REF_SRC			253
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define PCIE_1_ALT_REF_CLK			254
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define PCIE_2_A_CLK				255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define PCIE_2_AUX_CLK				256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define PCIE_2_H_CLK				257
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define PCIE_2_PHY_CLK				258
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define PCIE_2_ALT_REF_SRC			259
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define PCIE_2_ALT_REF_CLK			260
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define EBI2_CLK				261
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define USB30_SLEEP_CLK				262
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define USB30_UTMI_SRC				263
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define USB30_0_UTMI_CLK			264
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define USB30_1_UTMI_CLK			265
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define USB30_MASTER_SRC			266
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define USB30_0_MASTER_CLK			267
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define USB30_1_MASTER_CLK			268
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define GMAC_CORE1_CLK_SRC			269
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define GMAC_CORE2_CLK_SRC			270
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define GMAC_CORE3_CLK_SRC			271
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define GMAC_CORE4_CLK_SRC			272
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define GMAC_CORE1_CLK				273
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define GMAC_CORE2_CLK				274
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define GMAC_CORE3_CLK				275
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define GMAC_CORE4_CLK				276
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define UBI32_CORE1_CLK_SRC			277
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define UBI32_CORE2_CLK_SRC			278
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define UBI32_CORE1_CLK				279
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define UBI32_CORE2_CLK				280
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define EBI2_AON_CLK				281
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define NSSTCM_CLK_SRC				282
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define NSSTCM_CLK				283
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #endif