Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2018, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_6018_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #define _DT_BINDINGS_CLOCK_IPQ_GCC_6018_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #define GPLL0					0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #define UBI32_PLL				1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define GPLL6					2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define GPLL4					3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define PCNOC_BFDCD_CLK_SRC			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define GPLL2					5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define NSS_CRYPTO_PLL				6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define NSS_PPE_CLK_SRC				7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define GCC_XO_CLK_SRC				8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define NSS_CE_CLK_SRC				9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define GCC_SLEEP_CLK_SRC			10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define APSS_AHB_CLK_SRC			11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define NSS_PORT5_RX_CLK_SRC			12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define NSS_PORT5_TX_CLK_SRC			13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define PCIE0_AXI_CLK_SRC			14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define USB0_MASTER_CLK_SRC			15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define APSS_AHB_POSTDIV_CLK_SRC		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define NSS_PORT1_RX_CLK_SRC			17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define NSS_PORT1_TX_CLK_SRC			18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define NSS_PORT2_RX_CLK_SRC			19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define NSS_PORT2_TX_CLK_SRC			20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define NSS_PORT3_RX_CLK_SRC			21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define NSS_PORT3_TX_CLK_SRC			22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define NSS_PORT4_RX_CLK_SRC			23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define NSS_PORT4_TX_CLK_SRC			24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define NSS_PORT5_RX_DIV_CLK_SRC		25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define NSS_PORT5_TX_DIV_CLK_SRC		26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define APSS_AXI_CLK_SRC			27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define NSS_CRYPTO_CLK_SRC			28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define NSS_PORT1_RX_DIV_CLK_SRC		29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define NSS_PORT1_TX_DIV_CLK_SRC		30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define NSS_PORT2_RX_DIV_CLK_SRC		31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define NSS_PORT2_TX_DIV_CLK_SRC		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define NSS_PORT3_RX_DIV_CLK_SRC		33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define NSS_PORT3_TX_DIV_CLK_SRC		34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define NSS_PORT4_RX_DIV_CLK_SRC		35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define NSS_PORT4_TX_DIV_CLK_SRC		36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define NSS_UBI0_CLK_SRC			37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define BLSP1_QUP1_I2C_APPS_CLK_SRC		38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define BLSP1_QUP1_SPI_APPS_CLK_SRC		39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define BLSP1_QUP2_I2C_APPS_CLK_SRC		40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define BLSP1_QUP2_SPI_APPS_CLK_SRC		41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define BLSP1_QUP3_I2C_APPS_CLK_SRC		42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define BLSP1_QUP3_SPI_APPS_CLK_SRC		43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define BLSP1_QUP4_I2C_APPS_CLK_SRC		44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define BLSP1_QUP4_SPI_APPS_CLK_SRC		45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define BLSP1_QUP5_I2C_APPS_CLK_SRC		46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define BLSP1_QUP5_SPI_APPS_CLK_SRC		47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define BLSP1_QUP6_I2C_APPS_CLK_SRC		48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define BLSP1_QUP6_SPI_APPS_CLK_SRC		49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define BLSP1_UART1_APPS_CLK_SRC		50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define BLSP1_UART2_APPS_CLK_SRC		51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define BLSP1_UART3_APPS_CLK_SRC		52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define BLSP1_UART4_APPS_CLK_SRC		53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define BLSP1_UART5_APPS_CLK_SRC		54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define BLSP1_UART6_APPS_CLK_SRC		55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define CRYPTO_CLK_SRC				56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define NSS_UBI0_DIV_CLK_SRC			57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define PCIE0_AUX_CLK_SRC			58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define PCIE0_PIPE_CLK_SRC			59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define SDCC1_APPS_CLK_SRC			60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define USB0_AUX_CLK_SRC			61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define USB0_MOCK_UTMI_CLK_SRC			62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define USB0_PIPE_CLK_SRC			63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define USB1_MOCK_UTMI_CLK_SRC			64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define GCC_APSS_AHB_CLK			65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define GCC_APSS_AXI_CLK			66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define GCC_BLSP1_AHB_CLK			67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define GCC_BLSP1_QUP1_I2C_APPS_CLK		68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define GCC_BLSP1_QUP1_SPI_APPS_CLK		69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define GCC_BLSP1_QUP2_I2C_APPS_CLK		70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define GCC_BLSP1_QUP2_SPI_APPS_CLK		71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define GCC_BLSP1_QUP3_I2C_APPS_CLK		72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define GCC_BLSP1_QUP3_SPI_APPS_CLK		73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define GCC_BLSP1_QUP4_I2C_APPS_CLK		74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define GCC_BLSP1_QUP4_SPI_APPS_CLK		75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define GCC_BLSP1_QUP5_I2C_APPS_CLK		76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define GCC_BLSP1_QUP5_SPI_APPS_CLK		77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define GCC_BLSP1_QUP6_I2C_APPS_CLK		78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define GCC_BLSP1_QUP6_SPI_APPS_CLK		79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define GCC_BLSP1_UART1_APPS_CLK		80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define GCC_BLSP1_UART2_APPS_CLK		81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define GCC_BLSP1_UART3_APPS_CLK		82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define GCC_BLSP1_UART4_APPS_CLK		83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define GCC_BLSP1_UART5_APPS_CLK		84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define GCC_BLSP1_UART6_APPS_CLK		85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define GCC_CRYPTO_AHB_CLK			86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define GCC_CRYPTO_AXI_CLK			87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define GCC_CRYPTO_CLK				88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define GCC_XO_CLK				89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define GCC_XO_DIV4_CLK				90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define GCC_MDIO_AHB_CLK			91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define GCC_CRYPTO_PPE_CLK			92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define GCC_NSS_CE_APB_CLK			93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define GCC_NSS_CE_AXI_CLK			94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define GCC_NSS_CFG_CLK				95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define GCC_NSS_CRYPTO_CLK			96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define GCC_NSS_CSR_CLK				97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define GCC_NSS_EDMA_CFG_CLK			98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define GCC_NSS_EDMA_CLK			99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define GCC_NSS_NOC_CLK				100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define GCC_NSS_PORT1_RX_CLK			101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define GCC_NSS_PORT1_TX_CLK			102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define GCC_NSS_PORT2_RX_CLK			103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define GCC_NSS_PORT2_TX_CLK			104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define GCC_NSS_PORT3_RX_CLK			105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define GCC_NSS_PORT3_TX_CLK			106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define GCC_NSS_PORT4_RX_CLK			107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define GCC_NSS_PORT4_TX_CLK			108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define GCC_NSS_PORT5_RX_CLK			109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define GCC_NSS_PORT5_TX_CLK			110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define GCC_NSS_PPE_CFG_CLK			111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define GCC_NSS_PPE_CLK				112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define GCC_NSS_PPE_IPE_CLK			113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define GCC_NSS_PTP_REF_CLK			114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define GCC_NSSNOC_CE_APB_CLK			115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define GCC_NSSNOC_CE_AXI_CLK			116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define GCC_NSSNOC_CRYPTO_CLK			117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define GCC_NSSNOC_PPE_CFG_CLK			118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define GCC_NSSNOC_PPE_CLK			119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define GCC_NSSNOC_QOSGEN_REF_CLK		120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define GCC_NSSNOC_TIMEOUT_REF_CLK		121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define GCC_NSSNOC_UBI0_AHB_CLK			122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define GCC_PORT1_MAC_CLK			123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define GCC_PORT2_MAC_CLK			124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define GCC_PORT3_MAC_CLK			125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define GCC_PORT4_MAC_CLK			126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define GCC_PORT5_MAC_CLK			127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define GCC_UBI0_AHB_CLK			128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define GCC_UBI0_AXI_CLK			129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define GCC_UBI0_CORE_CLK			130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define GCC_PCIE0_AHB_CLK			131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define GCC_PCIE0_AUX_CLK			132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define GCC_PCIE0_AXI_M_CLK			133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define GCC_PCIE0_AXI_S_CLK			134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define GCC_PCIE0_PIPE_CLK			135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define GCC_PRNG_AHB_CLK			136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define GCC_QPIC_AHB_CLK			137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define GCC_QPIC_CLK				138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define GCC_SDCC1_AHB_CLK			139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define GCC_SDCC1_APPS_CLK			140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define GCC_UNIPHY0_AHB_CLK			141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define GCC_UNIPHY0_PORT1_RX_CLK		142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define GCC_UNIPHY0_PORT1_TX_CLK		143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define GCC_UNIPHY0_PORT2_RX_CLK		144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define GCC_UNIPHY0_PORT2_TX_CLK		145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define GCC_UNIPHY0_PORT3_RX_CLK		146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define GCC_UNIPHY0_PORT3_TX_CLK		147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define GCC_UNIPHY0_PORT4_RX_CLK		148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define GCC_UNIPHY0_PORT4_TX_CLK		149
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define GCC_UNIPHY0_PORT5_RX_CLK		150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define GCC_UNIPHY0_PORT5_TX_CLK		151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define GCC_UNIPHY0_SYS_CLK			152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define GCC_UNIPHY1_AHB_CLK			153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define GCC_UNIPHY1_PORT5_RX_CLK		154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define GCC_UNIPHY1_PORT5_TX_CLK		155
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define GCC_UNIPHY1_SYS_CLK			156
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define GCC_USB0_AUX_CLK			157
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define GCC_USB0_MASTER_CLK			158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define GCC_USB0_MOCK_UTMI_CLK			159
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define GCC_USB0_PHY_CFG_AHB_CLK		160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define GCC_USB0_PIPE_CLK			161
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define GCC_USB0_SLEEP_CLK			162
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define GCC_USB1_MASTER_CLK			163
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define GCC_USB1_MOCK_UTMI_CLK			164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define GCC_USB1_PHY_CFG_AHB_CLK		165
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define GCC_USB1_SLEEP_CLK			166
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define GP1_CLK_SRC				167
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define GP2_CLK_SRC				168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define GP3_CLK_SRC				169
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define GCC_GP1_CLK				170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define GCC_GP2_CLK				171
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define GCC_GP3_CLK				172
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define SYSTEM_NOC_BFDCD_CLK_SRC		173
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define GCC_NSSNOC_SNOC_CLK			174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define GCC_UBI0_NC_AXI_CLK			175
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define GCC_UBI1_NC_AXI_CLK			176
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define GPLL0_MAIN				177
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define UBI32_PLL_MAIN				178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define GPLL6_MAIN				179
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define GPLL4_MAIN				180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define GPLL2_MAIN				181
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define NSS_CRYPTO_PLL_MAIN			182
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define GCC_CMN_12GPLL_AHB_CLK			183
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define GCC_CMN_12GPLL_SYS_CLK			184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define GCC_SNOC_BUS_TIMEOUT2_AHB_CLK		185
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define GCC_SYS_NOC_USB0_AXI_CLK		186
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define GCC_SYS_NOC_PCIE0_AXI_CLK		187
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define QDSS_TSCTR_CLK_SRC			188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define QDSS_AT_CLK_SRC				189
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define GCC_QDSS_AT_CLK				190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define GCC_QDSS_DAP_CLK			191
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define ADSS_PWM_CLK_SRC			192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define GCC_ADSS_PWM_CLK			193
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define SDCC1_ICE_CORE_CLK_SRC			194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define GCC_SDCC1_ICE_CORE_CLK			195
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define GCC_DCC_CLK				196
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define PCIE0_RCHNG_CLK_SRC			197
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define GCC_PCIE0_AXI_S_BRIDGE_CLK		198
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define PCIE0_RCHNG_CLK				199
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define UBI32_MEM_NOC_BFDCD_CLK_SRC		200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define WCSS_AHB_CLK_SRC			201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define Q6_AXI_CLK_SRC				202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define GCC_Q6SS_PCLKDBG_CLK			203
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define GCC_Q6_TSCTR_1TO2_CLK			204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define GCC_WCSS_CORE_TBU_CLK			205
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define GCC_WCSS_AXI_M_CLK			206
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define GCC_SYS_NOC_WCSS_AHB_CLK		207
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define GCC_Q6_AXIM_CLK				208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define GCC_Q6SS_ATBM_CLK			209
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define GCC_WCSS_Q6_TBU_CLK			210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define GCC_Q6_AXIM2_CLK			211
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define GCC_Q6_AHB_CLK				212
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define GCC_Q6_AHB_S_CLK			213
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define GCC_WCSS_DBG_IFC_APB_CLK		214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define GCC_WCSS_DBG_IFC_ATB_CLK		215
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define GCC_WCSS_DBG_IFC_NTS_CLK		216
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define GCC_WCSS_DBG_IFC_DAPBUS_CLK		217
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define GCC_WCSS_DBG_IFC_APB_BDG_CLK		218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define GCC_WCSS_DBG_IFC_ATB_BDG_CLK		219
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define GCC_WCSS_DBG_IFC_NTS_BDG_CLK		220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define GCC_WCSS_DBG_IFC_DAPBUS_BDG_CLK		221
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define GCC_WCSS_ECAHB_CLK			222
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define GCC_WCSS_ACMT_CLK			223
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define GCC_WCSS_AHB_S_CLK			224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define GCC_RBCPR_WCSS_CLK			225
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define RBCPR_WCSS_CLK_SRC			226
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define GCC_RBCPR_WCSS_AHB_CLK			227
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define GCC_LPASS_CORE_AXIM_CLK			228
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define GCC_LPASS_SNOC_CFG_CLK			229
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define GCC_LPASS_Q6_AXIM_CLK			230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define GCC_LPASS_Q6_ATBM_AT_CLK		231
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define GCC_LPASS_Q6_PCLKDBG_CLK		232
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define GCC_LPASS_Q6SS_TSCTR_1TO2_CLK		233
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define GCC_LPASS_Q6SS_TRIG_CLK			234
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define GCC_LPASS_TBU_CLK			235
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define LPASS_CORE_AXIM_CLK_SRC			236
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define LPASS_SNOC_CFG_CLK_SRC			237
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define LPASS_Q6_AXIM_CLK_SRC			238
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define GCC_PCNOC_LPASS_CLK			239
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define GCC_UBI0_UTCM_CLK			240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define SNOC_NSSNOC_BFDCD_CLK_SRC		241
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define GCC_SNOC_NSSNOC_CLK			242
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define GCC_MEM_NOC_Q6_AXI_CLK			243
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define GCC_MEM_NOC_UBI32_CLK			244
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define GCC_MEM_NOC_LPASS_CLK			245
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define GCC_SNOC_LPASS_CFG_CLK			246
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define GCC_SYS_NOC_QDSS_STM_AXI_CLK		247
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define GCC_QDSS_STM_CLK			248
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define GCC_QDSS_TRACECLKIN_CLK			249
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define QDSS_STM_CLK_SRC			250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define QDSS_TRACECLKIN_CLK_SRC			251
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define GCC_NSSNOC_ATB_CLK			252
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #endif